The ispXPGA family of devices provides the ideal vehicle for the creation of high-performance logic designs that

are both non-volatile and infinitely re-programmable. Other FPGA solutions force a compromise, being either re-

programmable or non-volatile. This family couples this capability with a mainstream architecture containing the fea-

tures required for today's system-level design.

The ispXPGA family is available in two options. The standard device supports sysHSI capability for ultra fast serial

communications while the lower-cost "E-Series" supports the same high-performance FPGA fabric without the sys-

HSI Block.

Electrically Erasable CMOS (E2CMOS) memory cells provide the ispXPGA family with non-volatile capability.

These allow logic to be functional microseconds after power is applied, allowving easy interfacing in many applica-

tions. This capability also means that expensive external configuration memories are not required and that designs

can be secured from unauthorized read back. Internal SRAM cells allow the device to be infinitely reconfigured if

desired. Both the SRAM and E2CMOS cells can be programmed and veritied through the IEEE 1532 industry stan-

dard. Additionally, the SRAM cells can be configured and read-back through the sysCONFIGIM peripheral port.

The family spans the density and /0 range required for the majority of today's logic designs, 139K to1.25M func-

tional gates and 160 to 496 /O. The devices are available for operation from 1.8V, 2.5V, and3.3V power supplies,

providing easy integration into the overall system.

System-level design needs are met through the incorporation of sysMEM dual-port memory blocks, sysIO

advanced /O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications are sup-

ported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serialization

(SERDES).

The ispl EVERTM design tool from Lattice allws easy implementation of designs using the ispXPGA product. Syn-

thesis library support is available for major logic synthesis tools. The ispL EVER tool takes the output from these

common synthesis packages and place and routes the design in the ispXPGA product. The tool supports floor

planning and the management of other constraints within the device. The tool also provides outputs to common

timing analysis tools for timning analysi:

To increase designer productivity, Lattice provides avariety of pre-designed modules referred to as IP cores for the

ispXPGA product. These JIP cores allow designers to concentrate on the unique portions of their design while using

pre-designed blocks to implement standard functions such as bus interfaces, standard communication interfaces,

and memory controllers.

Through the use of advanced technology and jinnovative architecture the ispXPGA FPGA devices provide design-

ers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz.

Certain designs can run at over 300MHz. Table 2 details the performance of several building blocks commonly

used by logic designers.

Functional

Programmable Function Unit

The Programmable Function Unit (PFU) is the basic building block of the ispXPGA architecture. The PFUs are

arranged in rows and columns in the device with PFU (1,1) referring to (row1, column 1). Each PFU consists of

four Configurable Logic Elements (CLEs), four Configurable Sequential Elements (CSEs), and a Wide Logic Gen-

erator (WLG). By uilizing these components, the PFU can implement a variety of functions. Table 3 lists some of

the function capabilities of the PFU.

There are 57 inputs to each PFU and nine outputs. The PFU uses 20 inputs for logic, and 37 inputs drive the con-

trol logic from which six control signals are derived for the PFU.