LFX125EB-04F256I

LFX125EB-04F256I FPGAs Overview

The ispXPGA family of devices provides the ideal vehicle for the creation of high-performance logic designs that are both non-volatile and infinitely re-programmable. Other FPGA solutions force a compromise, being either reprogrammable or non-volatile. This family couples this capability with a mainstream architecture containing the features required for today���s system-level design. The Lattice FPGA - Field Programmable Gate Array series LFX125EB-04F256I is FPGA - Field Programmable Gate Array E-Series, 139K Gates, 160 I/O, ispJTAG, 2.5/3.3V, -4 Speed, IND, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

■ Non-volatile, Infinitely Reconfigurable

• Instant-on - Powers up in microseconds via on-chip E2 CMOS based memory

• No external configuration memory

• Excellent design security, no bit stream to intercept

• Reconfigure SRAM based logic in milliseconds

■ High Logic Density for System-level Integration

• 139K to 1.25M system gates

• 160 to 496 I/O

• 1.8V, 2.5V, and 3.3V VCC operation

• Up to 414Kb sysMEM embedded memory

■ High Performance Programmable Function Unit (PFU)

• Four LUT-4 per PFU supports wide and narrow functions

• Dual flip-flops per LUT-4 for extensive pipelining

• Dedicated logic for adders, multipliers, multiplexers, and counters

■ Flexible Memory Resources

• Multiple sysMEM Embedded RAM Blocks

– Single port, Dual port, and FIFO operation

• 64-bit distributed memory in each PFU

– Single port, Double port, FIFO, and Shift Register operation

■ Flexible Programming, Reconfiguration, and Testing

• Supports IEEE 1532 and 1149.1

• Microprocessor configuration interface

• Program E2 CMOS while operating from SRAM

■ Eight sysCLOCK Phase Locked Loops (PLLs) for Clock Management

• True PLL technology

• 10MHz to 320MHz operation

• Clock multiplication and division

• Phase adjustment

• Shift clocks in 250ps steps

■ sysIO for High System Performance

• High speed memory support through SSTL and HSTL

• Advanced buses supported through PCI, GTL+, LVDS, BLVDS, and LVPECL

• Standard logic supported through LVTTL, LVCMOS 3.3, 2.5 and 1.8

• 5V tolerant I/O for LVCMOS 3.3 and LVTTL interfaces

• Programmable drive strength for series termination

• Programmable bus maintenance

■ Two Options Available

• High-performance sysHSI (standard part number)

• Low-cost, no sysHSI (“E-Series”)

■ sysHSI Capability for Ultra Fast Serial Communications

• Up to 800Mbps performance

• Up to 20 channels per device

• Built in Clock Data Recovery (CDR) and Serialization and De-serialization (SERDES)