Description

The Lattice Semiconductor iCE65 programmable logic family is specifically designed to deliver the lowest static and dynamic power consumption of any comparable CPLD or FPGA device. iCE65 devices are designed for costsensitive, high-volume applications and provide on-chip, nonvolatile configuration memory (NVCM) to customize for a specific application. iCE65 devices can self-configure from a configuration image stored in an external commodity SPI serial Flash PROM or be downloaded from an external processor over an SPI-like serial port. The three iCE65 components, highlighted in Table 1, deliver from approximately 1K to nearly 8K logic cells and flipflops while consuming a fraction of the power of comparable programmable logic devices. Each iCE65 device includes between 16 to 32 RAM blocks, each with 4Kbits of storage, for on-chip data storage and data buffering.

As pictured in Figure 1, each iCE65 device consists of four primary architectural elements.

 An array of Programmable Logic Blocks (PLBs)

 Each PLB contains eight Logic Cells (LCs); each Logic Cell consists of …

 A fast, four-input look-up table (LUT4) capable of implementing any combinational logic function of up to four inputs, regardless of complexity

 A ‘D’-type flip-flop with an optional clock-enable and set/reset control

 Fast carry logic to accelerate arithmetic functions such as adders, subtracters, comparators, and    counters.

 Common clock input with polarity control, clock-enable input, and optional set/reset control input to

  the PLB is shared among all eight Logic Cells

 Two-port, 4Kbit RAM blocks (RAM4K)

 256x16 default configuration; selectable data width using programmable logic resources

 Simultaneous read and write access; ideal for FIFO memory and data buffering applications

 RAM contents pre-loadable during configuration

 Four I/O banks with independent supply voltage, each with multiple Programmable Input/Output (PIO)

   blocks

 LVCMOS I/O standards and LVDS outputs supported in all banks

 I/O Bank 3 supports additional SSTL, MDDR, LVDS, and SubLVDS I/O standards

 Programmable interconnections between the blocks

 Flexible connections between all programmable logic functions

 Eight dedicated low-skew, high-fanout clock distribution networks