ICE65L01F-TVQ100C

ICE65L01F-TVQ100C FPGAs Overview

The Lattice Semiconductor iCE65 programmable logic family is specifically designed to deliver the lowest static and dynamic power consumption of any comparable CPLD or FPGA device. iCE65 devices are designed for costsensitive, high-volume applications and provide on-chip, nonvolatile configuration memory (NVCM) to customize for a specific application. iCE65 devices can self-configure from a configuration image stored in an external commodity SPI serial Flash PROM or be downloaded from an external processor over an SPI-like serial port. The three iCE65 components, highlighted in ICE65L01F-TVQ100C Datasheet, deliver from approximately 1K to nearly 8K logic cells and flipflops while consuming a fraction of the power of comparable programmable logic devices. Each iCE65 device includes between 16 to 32 RAM blocks, each with 4Kbits of storage, for on-chip data storage and data buffering. As pictured in ICE65L01F-TVQ100C Diagram, each iCE65 device consists of four primary architectural elements.

 An array of Programmable Logic Blocks (PLBs)

 Each PLB contains eight Logic Cells (LCs); each Logic Cell consists of …

 A fast, four-input look-up table (LUT4) capable of implementing any combinational logic function of up to four inputs, regardless of complexity

 A ‘D’-type flip-flop with an optional clock-enable and set/reset control

 Fast carry logic to accelerate arithmetic functions such as adders, subtracters, comparators, and counters.

 Common clock input with polarity control, clock-enable input, and optional set/reset control input to the PLB is shared among all eight Logic Cells

 Two-port, 4Kbit RAM blocks (RAM4K)

 256x16 default configuration; selectable data width using programmable logic resources

 Simultaneous read and write access; ideal for FIFO memory and data buffering applications

 RAM contents pre-loadable during configuration

 Four I/O banks with independent supply voltage, each with multiple Programmable Input/Output (PIO) blocks

 LVCMOS I/O standards and LVDS outputs supported in all banks

 I/O Bank 3 supports additional SSTL, MDDR, LVDS, and SubLVDS I/O standards

 Programmable interconnections between the blocks

 Flexible connections between all programmable logic functions

 Eight dedicated low-skew, high-fanout clock distribution networks

The Lattice Programmable Logic ICs series ICE65L01F-TVQ100C is FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

 First high-density, ultra low-power single-chip, SRAM mobileFPGA family specifically designed for hand-held applications and long battery life

 12 µA in static mode

 Two power/speed options –L: Low Power –T: High speed

 Up to 256 MHz internal performance

 Reprogrammable from a variety of sources and methods

 Processor-like mode self-configures from external, commodity SPI serial Flash PROM

 Downloaded by processor using SPI-like serial interface in as little as 20 µs

 In-system programmable, ASIC-like mode loads from secure, internal Nonvolatile Configuration Memory (NVCM)

 Ideal for volume production

 Superior design and intellectual property protection; no exposed data

 Proven, high-volume 65 nm, low-power CMOS technology

 Low leakage, µW static power

 Lower core voltage, lowest dynamic power

 Flexible programmable logic and programmable interconnect fabric

 Over 7,600 look-up tables (LUT4) and flip-flops

 Low-power logic and interconnect

 Flexible I/O pins to simplify system interfaces

 Up to 222 programmable I/O pins

 Four independently-powered I/O banks; support for 3.3V, 2.5V, 1.8V, and 1.5V voltage standards

 LVCMOS, MDDR, LVDS, and SubLVDS I/O standards

 Plentiful, fast, on-chip 4Kbit RAM blocks

 Low-cost, space-efficient packaging options

 Known-good die (KGD) options available

 Complete iCEcube development system

 Windows and Linux support

 VHDL and Verilog logic synthesis

 Place and route software

 Design and IP core libraries

 Low-cost iCEman65 development board