iCE40 UltraPlus family from Lattice Semiconductor is an ultra-low power FPGA and sensor manager designed for ultra-low power mobile applications, such as smartphones, tablets and hand-held devices. iCE40 UltraPlus is compatible with Lattice's iCE40 Ultra family devices, containing all the functions iCE40 Ultra family has except the high current IR LED driver. In addition, the iCE40 UltraPlus features an additional 1 Mb SRAM, additional DSP blocks, with additional LUTs, all which can be used to support an always-on Voice Recognition function in the mobile devices, without the need to keep the higher power consuming voice codec on all the time. The iCE40 UltraPlus family includes integrated SPI and I 2 C blocks to interface with virtually all mobile sensors and application processors. In addition, the iCE40 UltraPlus family also features two I/O pins that can support the interface to I3C devices. There are two on-chip oscillators, 10 kHz and 48 MHz, the LFOSC (10 kHz) is ideal for low power function in always-on applications, while HFOSC (48 MHz) can be used for awaken activities. The iCE40 UltraPlus family also features DSP functional block to off-load Application Processor to pre-process information sent from the mobile device, such as voice data. The RGB PWM IP, with the three 24 mA constant current RGB outputs on the iCE40 UltraPlus provides all the necessary logic to directly drive the service LED, without the need of external MOSFET or buffer. The iCE40 UltraPlus family of devices are targeting for mobile applications to perform all the functions in iCE40 Ultra devices, such as Service LED, GPIO Expander, SDIO Level Shift, and other custom functions. In addition, the iCE40 UltraPlus family devices are also targeting for Voice Recognition application. The iCE40 UltraPlus family features two device densities, 2800 to 5280 Look Up Tables (LUTs) of logic with programmable I/Os that can be used as either SPI/I2C interface ports or general purpose I/O’s. Two of the iCE40 UltraPlus I/Os can be used to interface to higher performance I3C. It also has up to 120 kb of Block RAMs, plus 1024 kb of Single Port SRAMs to work with user logic.

Functional

The iCE40 UltraPlus family architecture contains an array of Programmable Logic Blocks (PLB), two Oscillator Generators, two user configurable I2 C controllers, two user configurable SPI controllers, blocks of sysMEM Embedded Block RAM (EBR) and Single Port RAM (SPRAM) surrounded by Programmable I/O (PIO). Figure 3.1 shows the block diagram of the iCE40UP5K device.The Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows and columns. Each column has either PLB or EBR blocks. The PIO cells are located at the top and bottom of the device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. In the iCE40 UltraPlus family, there are three sysIO banks, one on top and two at the bottom. User can connect some VCCIOs together, if all the I/Os are using the same voltage standard. See the Power-up Supply Sequence section. The sysMEM EBRs are large 4 kb, dedicated fast memory blocks. These blocks can be configured as RAM, ROM or FIFO with user logic using PLBs. In addition to the EBR, the iCE40 UltraPlus devices also feature four 256 kb SPRAM blocks that can be cascaded to create up to 1 Mb block. It is useful for temporary storage of large quantities of information.

Features

 Flexible Logic Architecture

 Two devices with 2800 to 5280 LUTs

 Offered in WLCS and QFN packages

 Ultra-low Power Devices

 Advanced 40 nm low power process

 As low as 100 µA standby current typical

 Embedded Memory

 Up to 1024 kb Single Port SRAM

 Up to 120 kb sysMEM Embedded Block RAM

 Two Hardened I2C Interfaces

 Two I/O pins to support I3C interface

 Two Hardened SPI Interfaces

 Two On-Chip Oscillators

 Low Frequency Oscillator – 10 kHz

 High Frequency Oscillator – 48 MHz

 24 mA Current Drive RGB LED Outputs

 Three drive outputs in each device

 User selectable sink current up to 24 mA

 On-chip DSP

 Signed and unsigned 8-bit or 16-bit functions

 Functions include Multiplier, Accumulator, and

  Multiply-Accumulate (MAC)

 Flexible On-Chip Clocking

 Eight low skew global signal resource, six can be directly driven from external pins

 One PLL with dynamic interface per device

 Flexible Device Configuration

 SRAM is configured through:

 Standard SPI Interface

 Internal Nonvolatile Configuration Memory (NVCM)

 Ultra-Small Form Factor

 As small as 2.11 mm × 2.54 mm

 Applications

 Always-On Voice Recognition Application

 Smartphones

 Tablets and Consumer Handheld Devices

 Handheld Commercial and Industrial Devices

 Multi Sensor Management Applications

 Sensor Pre-processing and Sensor Fusion

 Always-On Sensor Applications

 USB 3.1 Type C Cable Detect / Power Delivery Applications