ICE40UL1K-CM36AITR1K FPGAs Overview
The iCE40 family of ultra-low power, non-volatile FPGAs has five devices with densities ranging from 384 to 7680 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic, these devices feature Embedded Block RAM (EBR), Non-volatile Configuration Memory (NVCM) and Phase Locked Loops (PLLs). These features allow the devices to be used in low-cost, high-volume consumer and system applications. Select packages offer High-Current drivers that are ideal to drive three white LEDs, or one RGB LED. The iCE40 devices are fabricated on a 40 nm CMOS low power process. The device architecture has several features such as programmable low-swing differential I/Os and the ability to turn off on-chip PLLs dynamically. These features help manage static and dynamic power consumption, resulting in low static power for all members of the family. The iCE40 devices are available in two versions – ultra low power (LP) and high performance (HX) devices. The iCE40 FPGAs are available in a broad range of advanced halogen-free packages ranging from the space saving 1.40x1.48 mm WLCSP to the PCB-friendly 20x20 mm TQFP. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters. The iCE40 devices offer enhanced I/O features such as pull-up resistors. Pull-up features are controllable on a “per-pin” basis. The iCE40 devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices can also configure themselves from external SPI Flash or be configured by an external master such as a CPU. Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40 family of devices. Popular logic synthesis tools provide synthesis library support for iCE40. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the iCE40 device. These tools extract the timing from the routing and back-annotate it into the design for timing verification. Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs, licensed free of charge, optimized for the iCE40 FPGA family. By using these configurable soft core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity.
The Lattice FPGAs (Field Programmable Gate Array) series ICE40UL1K-CM36AITR1K is IC FPGA ULTRA 1.2V 36UCBGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com,
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Features
Flexible Logic Architecture
Two devices with 2800 to 5280 LUTs
Offered
in WLCS and QFN packages
Ultra-low Power Devices
Advanced 40 nm low power
process
As low as 100 µA standby current typical
Embedded Memory
Up to
1024 kb Single Port SRAM
Up to 120 kb sysMEM Embedded Block RAM
Two
Hardened I2C Interfaces
Two I/O pins to support I3C interface
Two Hardened
SPI Interfaces
Two On-Chip Oscillators
Low Frequency Oscillator – 10 kHz
High Frequency Oscillator – 48 MHz
24 mA Current Drive RGB LED Outputs
Three
drive outputs in each device
User selectable sink current up to 24 mA
On-chip DSP
Signed and unsigned 8-bit or 16-bit functions
Functions include
Multiplier, Accumulator, and Multiply-Accumulate (MAC)
Flexible On-Chip
Clocking
Eight low skew global signal resource, six can be directly driven
from external pins
One PLL with dynamic interface per device
Flexible Device
Configuration
SRAM is configured through:
Standard SPI Interface
Internal
Nonvolatile Configuration Memory (NVCM)
Ultra-Small Form Factor
As small as
2.15 mm × 2.55 mm
Applications
Always-On Voice Recognition Application
Smartphones
Tablets and Consumer Handheld Devices
Handheld Commercial and
Industrial Devices
Multi Sensor Management Applications
Sensor
Pre-processing and Sensor Fusion
Always-On Sensor Applications
USB 3.1 Type
C Cable Detect / Power Delivery Applications