Manufacturer | Xilinx |
Mounting Type | Surface Mount |
Number of I/O | 158 |
Package / Case | 240-BFQFP Exposed Pad |
Product Status | Obsolete |
Total RAM Bits | 294912 |
Number of Gates | 985882 |
Voltage - Supply | 1.71V ~ 1.89V |
Number of LABs/CLBs | 3456 |
Operating Temperature | 0°C ~ 85°C (TJ) |
Supplier Device Package | 240-PQFP (32x32) |
Number of Logic Elements/Cells | 15552 |
- Supported by free Synthesizable reference design
• High-Performance Built-In Clock Management Circuitry
- Eight fully digital Delay-Locked Loops (DLLs)
- Digitally-Synthesized 50% duty cycle for DoubleData Rate (DDR) Applications
- Clock Multiply and Divide
- Zero-delay conversion of high-speed LVPECL/LVDS clocks to any I/O standard
• Flexible Architecture Balances Speed and Density
- Dedicated carry logic for high-speed arithmetic
- Dedicated multiplier support
- Cascade chain for wide-input function
- Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset
- Internal 3-state bussing
- IEEE 1149.1 boundary-scan logic
- Die-temperature sensor diode
• Supported by Xilinx Foundation™ and Alliance Series™ Development Systems
- Further compile time reduction of 50%
- Internet Team Design (ITD) tool ideal for million-plus gate density designs
- Wide selection of PC and workstation platforms
• SRAM-Based In-System Configuration
- Unlimited re-programmability
• Advanced Packaging Options
- 0.8 mm Chip-scale
- 1.0 mm BGA
- 1.27 mm BGA
- HQ/PQ
• 0.18 mm 6-Layer Metal Process
• 100% Factory Tested
RF Data Converter Subsystem Overview
Most Zynq UltraScale+ RFSoCs include an RF data converter subsystem, which contains multiple radio frequency analog to digital converters (RF-ADCs) and multiple radio frequency digital to analog converters (RF-DACs). The high-precision, high-speed, power efficient RF-ADCs and RF-DACs can be individually configured for real data or can be configured in pairs for real and imaginary I/Q data.
Soft Decision Forward Error Correction (SD-FEC) Overview
Some Zynq UltraScale+ RFSoCs include highly flexible soft-decision FEC blocks for decoding and encoding data as a means to control errors in data transmission over unreliable or noisy communication channels. The SD-FEC blocks support low-density parity check (LDPC) decode/encode and Turbo decode for use in 5G wireless, backhaul, DOCSIS, and LTE applications.
Processing System Overview
Zynq UltraScale+ MPSoCs and RFSoCs feature dual and quad core variants of the Arm Cortex-A53 (APU) with dual-core Arm Cortex-R5F (RPU) processing system (PS). Some devices also include a dedicated Arm Mali-400 MP2 graphics processing unit (GPU).
Xilinx is a leading provider of programmable logic devices and associated technologies. As a top producer of programmable FPGAs, SoCs, MPSoCs, and 3D ICs, Xilinx has expanded quickly. Software defined and hardware optimized applications are supported by Xilinx, advancing the fields of cloud computing, SDN/NFV, video/vision, industrial IoT, and 5G wireless.
One of Xilinx's key innovations is the development of the Xilinx Vivado Design Suite, a comprehensive software toolchain used for designing and programming their FPGAs and SoCs. This suite provides developers with the necessary tools to create, simulate, and implement their designs on Xilinx devices.
In October 2020, Xilinx was acquired by Advanced Micro Devices (AMD), a major player in the semiconductor industry. This acquisition has enabled AMD to enhance its product portfolio and expand its offerings into the rapidly growing FPGA market.