Manufacturer | Xilinx® |
Series | XC9500 |
Packaging | Tray |
Manufacturer | Xilinx® |
Mounting Type | Surface Mount |
Number of I/ O | 72 |
Package / Case | 100-BQFP |
Product Status | Obsolete |
Number of Gates | 1600 |
Programmable Type | In System Programmable (min 10K program/erase cycles) |
Base Product Number | XC9572 |
Number of Macrocells | 72 |
Delay Time tpd(1) Max | 10 ns |
Operating Temperature | 0°C ~ 70°C (TA) |
Supplier Device Package | 100-PQFP (20x14) |
Integrated Circuits (ICs) | Embedded - CPLDs (Complex Programmable Logic Devices) |
Voltage Supply - Internal | 4.75V ~ 5.25V |
Number of Logic Elements/ Blocks | 4 |
The XC9572-10PQG100C is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns.
Power Management Power dissipation can be reduced in the XC9572-10PQG100C by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation.
Features
• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
• 72 macrocells with 1,600 usable gates
• Up to 72 user I/O pins
• 5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells within Function Block
- Global and product term clocks, output enables, set and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
• Programmable power reduction mode in each macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3V or 5V I/O capability
• Advanced CMOS 5V FastFLASH™ technology
• Supports parallel programming of more than one XC9500 concurrently
• Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP, and 100-pin TQFP packages
Description:
The XC9572 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns.
Power Management Power dissipation can be reduced in the XC9572 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation.
Features:
• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
• 72 macrocells with 1,600 usable gates
• Up to 72 user I/O pins
• 5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells within Function Block
- Global and product term clocks, output enables, set and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
• Programmable power reduction mode in each macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3V or 5V I/O capability
• Advanced CMOS 5V FastFLASH™ technology
• Supports parallel programming of more than one XC9500 concurrently
• Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP, and 100-pin TQFP packages