Manufacturer | Xilinx® |
Series | XC9500 |
Packaging | 84-LCC (J-Lead) |
Manufacturer | Xilinx® |
Numberof I/ O | 69 |
Numberof Gates | 1600 |
Product Status | Obsolete |
Programmable Type | In System Programmable (min 10K program/erase cycles) |
Numberof Macrocells | 72 |
Delay Timetpd(1) Max | 10 ns |
Operating Temperature | 0°C ~ 70°C (TA) |
Voltage Supply- Internal | 4.75V ~ 5.25V |
Integrated Circuits (ICs) | Embedded - CPLDs (Complex Programmable Logic Devices) |
Numberof Logic Elements/ Blocks | 4 |
Description
The XC9572-10PCG84C is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.
Features
• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
• 72 macrocells with 1,600 usable gates
• Up to 72 user I/O pins
• 5V in-system programmable
- Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells within Function Block
- Global and product term clocks, output enables, set and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
• Programmable power reduction mode in each macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3V or 5V I/O capability
• Advanced CMOS 5V FastFLASH™ technology
• Supports parallel programming of more than one XC9500 concurrently
• Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP, and 100-pin TQFP package
72 macrocells with 1,600 usable gates
Available in small footprint packages
44-pin VQFP (34 user I/O pins)
100-pin TQFP (72-user I/O pins)
Optimized for high-performance 2.5V systems
Low power operation
Multi-voltage operation
Advanced system features
In-system programmable
Superior pin-locking and routability with Fast CONNECT II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with individual product-term allocation
Local clock inversion with three global and one product-term clocks
Individual output enable per output pin
Input hysteresis on all user and boundary-scan pin inputs
Bus-hold ciruitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
20 year data retention
ESD protection exceeding 2,000V