XC7A35T-L1CPG236I

XC7A35T-L1CPG236I FPGAs Overview

Xilinx 7 series XC7A35T-L1CPG236I FPGAs families complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications.

Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, XC7A35T-L1CPG236I FPGAs enable an unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.

The Xilinx Embedded - FPGAs (Field Programmable Gate Array) series XC7A35T-L1CPG236I is Artix-7 FPGAFPGA 106 I/O 236BGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

• Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory.

• 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.

• High-performance SelectIO technology with support for DDR3 interfaces up to 1,866 Mb/s.

• High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to maximum rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.

• A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.

• DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering.

• Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.

• Integrated block for PCI Express (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.

• Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.