XC6VHX565T-2FFG1924E

XC6VHX565T-2FFG1924E FPGAs Overview

The XC6VHX565T-2FFG1924E FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins. Using the third-generation ASMBL (Advanced Silicon Modular Block) column-based architecture, the Xilinx XC6VHX565T-2FFG1924E contain many builtin system-level blocks. These features allow logic designers to build the highest levels of performance and functionality into their FPGAbased systems. Built on a 40 nm state-of-the-art copper process technology, XC6VHX565T-2FFG1924E FPGAs are a programmable alternative to custom ASIC technology. offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, connectivity, and soft microprocessor capabilities.

The Xilinx Embedded - FPGAs (Field Programmable Gate Array) series XC6VHX565T-2FFG1924E is Virtex-6 HXT FPGA 640 I/O 1924FCBGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

• Powerful mixed-mode clock managers (MMCM)

• MMCM blocks provide zero-delay buffering, frequency synthesis, clock-phase shifting, inputjitter filtering, and phase-matched clock division

• 36-Kb block RAM/FIFOs

• Dual-port widths up to 36 bits

• Simple dual-port widths up to 72 bits

• Dual-port RAM blocks

• Programmable

• Enhanced programmable FIFO logic

• Built-in optional error-correction circuitry

• Optionally use each block as two independent 18 Kb blocks

• High-performance parallel SelectIO technology

• 1.2 to 2.5V I/O operation

• Source-synchronous interfacing using ChipSync technology

• Digitally controlled impedance (DCI) active termination

• Flexible fine-grained I/O banking

• High-speed memory interface support with integrated write-leveling capability

• Advanced DSP48E1 slices

• Flexible configuration options

• System Monitor capability on all devices

• On-chip/off-chip thermal and supply voltage monitoring

• JTAG access to all monitored quantities

• Integrated interface blocks for PCI Express designs

• Compliant to the PCI Express Base Specification 2.0

• Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) support with GTX transceivers

• Endpoint and Root Port capable

• X1, x2, x4, or x8 lane support per block

• GTX transceivers: up to 6.6 Gb/s

• Data rates below 480 Mb/s supported by oversampling in FPGA logic.

• GTH transceivers: 2.488 Gb/s to beyond 11 Gb/s

• Integrated 10/100/1000 Mb/s Ethernet MAC block

• 40 nm copper CMOS process technology

• 1.0V core voltage (-1, -2, -3 speed grades only)

• Lower-power 0.9V core voltage option (-1L speed grade only)

• High signal-integrity flip-chip packaging available in standard or Pb-free package options