XC4028EX-4HQ208C

XC4028EX-4HQ208C FPGAs Overview

Introduction:

XC4000 Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of thirteen years of FPGA design experience and feedback from thousands of customers, these FPGAs combine architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs.

 Features:
• Highest Performance 

— 3.3 V XC4000XL 

• Highest Capacity 

— Over 180,000 Usable Gates 

• 5 V tolerant I/Os on XC4000XL 

• 0.35 µm SRAM process for XC4000XL 

• Additional Routing Over XC4000E - almost twice the routing capacity for high-density designs 

• Buffered Interconnect for Maximum Speed Blocks 

• Improved VersaRingTM I/O Interconnect for Better Fixed Pinout Flexibility 

• 12 mA Sink Current Per XC4000X Output 

• Flexible New High-Speed Clock Network 

- Eight additional Early Buffers for shorter clock delays 

- Virtually unlimited number of clock signals 

• Optional Multiplexer or 2-input Function Generator on Device Outputs 

• Four Additional Address Bits in Master Parallel Configuration Mode 

• XC4000XV Family offers the highest density with 0.25 µm 2.5 V technology

The Xilinx Socle de fusible series XC4028EX-4HQ208C is Field Programmable Gate Array (FPGA), View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

• Low-cost, register/latch rich, SRAM based reprogrammable architecture

- 0.5µm three-layer metal CMOS process technology

- 256 to 1936 logic cells (3,000 to 23,000 “gates”)

- Price competitive with Gate Arrays

• System Level Features

- System performance beyond 50 MHz

- 6 levels of interconnect hierarchy

- VersaRing I/O Interface for pin-locking

- Dedicated carry logic for high-speed arithmetic functions

- Cascade chain for wide input functions

- Built-in IEEE 1149.1 JTAG boundary scan test circuitry on all I/O pins

- Internal 3-state bussing capability

- Four dedicated low-skew clock or signal distribution nets

• Versatile I/O and Packaging

- Innovative VersaRing I/O interface provides a high logic cell to I/O ratio, with up to 244 I/O signals

- Programmable output slew-rate control maximizes performance and reduces noise

- Zero Flip-Flop hold time for input registers simplifies system timing

- Independent Output Enables for external bussing