Manufacturer | Rochester Electronics, LLC |
Mounting Type | Surface Mount |
Number of I/O | 77 |
Package / Case | 100-TQFP |
Product Status | Obsolete |
Total RAM Bits | 6272 |
Number of Gates | 5000 |
Voltage - Supply | 3V ~ 3.6V |
Number of LABs/CLBs | 196 |
Operating Temperature | 0°C ~ 85°C (TJ) |
Supplier Device Package | 100-VQFP (14x14) |
Number of Logic Elements/Cells | 466 |
For readers already familiar with the XC4005XL-1VQ100C of Xilinx Field Programmable Gate Arrays, the major new features in the XC4000 Series devices are listed in this section. The biggest advantages of XC4000E and XC4000X devices are significantly increased system speed, greater capacity, and new architectural features, particularly Select-RAM memory. The XC4000X devices also offer many new routing features, including special high-speed clock buffers that can be used to capture input data with minimal delay.
XC4005XL-1VQ100C device is pinout- and bitstream-compatible with the corresponding XC4000 device. An existing XC4000 bitstream can be used to program an XC4000E device. However, since the XC4000E includes many new features, an XC4000E bitstream cannot be loaded into an XC4000 device.
The Xilinx FPGAs series XC4005XL-1VQ100C is XC4000E and XC4000X Series Field Programmable Gate Arrays, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.• High Performance — 3.3 V XC4000XL
• High Capacity — Over 180,000 Usable Gates
• 5 V tolerant I/Os on XC4000XL
• 0.35 µm SRAM process for XC4000XL
• Additional Routing Over XC4000E
- almost twice the routing capacity for high-density designs
• Buffered Interconnect for Maximum Speed Blocks
• Improved VersaRingTM I/O Interconnect for Better Fixed Pinout Flexibility
• 12 mA Sink Current Per XC4000X Output
• Flexible New High-Speed Clock Network
- Eight additional Early Buffers for shorter clock delays
- Virtually unlimited number of clock signals
• Optional Multiplexer or 2-input Function Generator on Device Outputs
• Four Additional Address Bits in Master Parallel Configuration Mode