XC3042-100PQ100C

XC3042-100PQ100C FPGAs Overview

The CMOS XC3042-100PQ100C of Logic Cell Array (LCA) families provide a group of high-performance, high-density, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is com· posed of a configuration program store plus three types of configurable elements: a perimeter of 1/0 Blocks (lOBs), a core array of Configurable Logic Bocks (CLBs) and re· sources for interconnection. The general structure of an LCA device is shown in XC3042-100PQ100C Diagram on the next page. The XACT development system provides schematic capture and auto place-and-route for design entry. Logic and timing simulation, and in-circuit emulation are available as design verification alternatives. The design editor is used for interactive design optimization, and to compile the data pattern that represents the configuration program.

The LCA user logic functions and interconnections are determined by the configuration program data stored in internal static memory cells. The program can be loaded in any of several modes to accommodate various system requirements. The program data resides externally in an EEPROM, EPROM or ROM on the application circuit board, or on a floppy disk or hard disk. On-chip initialization logic provides for optional automatic loading of program data at power-up. The companion XC17XX Serial Configuration PROMs provide a very simple serial config· uration program storage in a one-lime programmable package.

The Xilinx FPGAs (Field Programmable Gate Array) series XC3042-100PQ100C is Field Programmable Gate Array (FPGA), View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

• Ideal for a wide range of custom VLSI design tasks
- Replaces TTL, MSI, and other PLD logic
- Integrates complete sub-systems into a single package
- Avoids the NRE, time delay, and risk of conventional masked gate arrays
• High-performance CMOS static memory technology
- Guaranteed toggle rates of 70 to 325 MHz, logic delays from 9 to 2.2 ns
- System clock speeds over 80 MHz
- Low quiescent and active power consumption
• Flexible FPGA architecture
- Compatible arrays ranging from 1,000 to 7,500 gate complexity
- Extensive register, combinatorial, and 1/0 capabilities
- High fan-out signal distribution, low-skew clock nets
- Internal 3-state bus capabilities
- TTL or CMOS input thresholds
- On-chip crystal oscillator amplifier
• Unlimited reprogrammability
- Easy design iteration
- In-system logic changes
• Extensive Packaging Options
- Over 20 different packages
- Plastic and ceramic surface-mount and pin-grid· array packages
- Thin and Very Thin Quad Flat Pack (TQFP and VQFP) options
• Ready for volume production
- Standard, off-the-shelf product availability
- 100% factory pre-tested devices

- Excellent reliability record

• Complete XACT Development System
- Schematic capture, automatic place and route
- Logic and timing simulation
- Interactive design editor for design optimization
- Timing calculator
- Interfaces to popular design environments like Viewlogic, Cadence, Mentor Graphics, and others