XC2VP50-7FFG1152C

XC2VP50-7FFG1152C FPGAs Overview

The Virtex-II Pro and Virtex-II Pro X families contain platform FPGAs for designs that are based on IP cores and customized modules. The family incorporates multi-gigabit transceivers and PowerPC CPU blocks in Virtex-II Pro Series FPGA architecture. It empowers complete solutions for telecommunication, wireless, networking, video, and DSP applications. 

The leading-edge 0.13 µm CMOS nine-layer copper process and Virtex-II Pro architecture are optimized for high performance designs in a wide range of densities. Combining a wide variety of flexible features and IP cores, the Virtex-II Pro family enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gate arrays. 

Features

This section briefly describes Virtex-II Pro / Virtex-II Pro X features. For more details, refer to Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description. 

RocketIO / RocketIO X MGT Cores 

The RocketIO and RocketIO X Multi-Gigabit Transceivers are flexible parallel-to-serial and serial-to-parallel embedded transceiver cores used for high-bandwidth interconnection between buses, backplanes, or other subsystems. Multiple user instantiations in an FPGA are possible, providing up to 100 Gb/s (RocketIO) or 170 Gb/s (RocketIO X) of full-duplex raw data transfer. Each channel can be operated at a maximum data transfer rate of 3.125 Gb/s (RocketIO) or 6.25 Gb/s (RocketIO X). Each RocketIO or RocketIO X core implements the following technology: 

• Serializer and deserializer (SERDES) 

• Monolithic clock synthesis and clock recovery (CDR) 

• 10 Gigabit Attachment Unit Interface (XAUI) Fibre Channel (3.1875 Gb/s XAUI), Infiniband, PCI Express, Aurora, SXI-5 (SFI-5,/SPI-5), and OC-48 compatibility(1) 

• 8/16/32-bit (RocketIO) or 8/16/32/64-bit (RocketIO X) selectable FPGA interface 

• 8B/10B (RocketIO) or 8B/10B and 64B/66B (RocketIO X) encoder and decoder with bypassing option on each channel 

• Channel bonding support (two to twenty channels) - Elastic buffers for inter-chip deskewing and channel-to-channel alignment • Receiver clock recovery tolerance of up to 75 non-transitioning bits 

• 50Ω (RocketIO X) or 50Ω /75Ω selectable (RocketIO) on-chip transmit and receive terminations 

• Programmable comma detection and word alignment 

• Rate matching via insertion/deletion characters 

• Automatic lock-to-reference function 

• Programmable pre-emphasis support 

• Per-channel serial and parallel transmitter-to-receiver internal loopback modes 

• Optional transmit and receive data inversion 

• Cyclic Redundancy Check support (RocketIO only)

The Xilinx FPGAs series XC2VP50-7FFG1152C is FPGA Virtex-II Pro Family 53136 Cells 1350MHz 0.13um/90nm (CMOS) Technology 1.5V 1152Pin FC-BGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

• High-Performance Platform FPGA Solution, Including

• Up to twenty RocketIO or RocketIO X embedded Multi-Gigabit Transceivers (MGTs)

• Up to two IBM PowerPC RISC processor blocks

• Based on Virtex-II Platform FPGA Technology

• Flexible logic resources

• SRAM-based in-system configuration

• Active Interconnect technology

• SelectRAM+ memory hierarchy

• Dedicated 18-bit x 18-bit multiplier blocks

• High-performance clock management circuitry

• SelectI/O-Ultra technology

• XCITE Digitally Controlled Impedance (DCI) I/O