XC2S150-5FG456C

XC2S150-5FG456C FPGAs Overview

Functional Description 
DS001-2(v2.8) June 13,2008
·Architectural Description
-Spartan-ll Array
-Input/Output Block
-Configurable Logic Block
-Block RAM
-Clock Distribution: Delay-Locked Loop
-Boundary Scan
·Development System
·Configuration
-Configuration Timing
·Design Considerations
Introduction 
The Spartan@. ll Field-Programmable Gate Array family gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The six-member family offers densities ranging from 15,000 to 200,000 system gates, as shown in Table 1. System performance is supported up to 200 MHz. Features includeblock RAM(to 56K bits), distributed RAM(to 75,264 bits), 16 selectable l/O standards, and four DLLs. Fast, predictable interconnect means that successive design iterations continue to meet timing requirements.
The Spartan-ll family is a superior alternative to mask-programmed ASICs. The FPGA avoids the initial cost, lengthy development cycles, and inherent risk ofconventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary(impossible with ASICs).
Features
·Second generation ASIC replacement technology
-Densities as high as 5,292 logic cells with up to
200,000 system gates
-Streamlined features based on Virtex? FPGA architecture
-Unlimited reprogrammability
-Very low cost
-Cost-effective 0.18 micron process

The Xilinx FPGAs series XC2S150-5FG456C is FPGA Spartan-II Family 150K Gates 3888 Cells 263MHz 0.18um Technology 2.5V 456Pin FBGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

• Second generation ASIC replacement technology

- Densities as high as 5,292 logic cells with up to 200,000 system gates

- Streamlined features based on Virtex FPGA architecture

- Unlimited reprogrammability

- Very low cost

- Cost-effective 0.18 micron process