Manufacturer | Xilinx |
Mounting Type | Surface Mount |
Number of I/O | 173 |
Package / Case | 208-BFQFP |
Product Status | Obsolete |
Number of Gates | 12000 |
Programmable Type | In System Programmable |
Number of Macrocells | 512 |
Delay Time tpd(1) Max | 9.2 ns |
Operating Temperature | -40°C ~ 85°C (TA) |
Supplier Device Package | 208-PQFP (28x28) |
Voltage Supply - Internal | 1.7V ~ 1.9V |
Number of Logic Elements/Blocks | 32 |
Description
The CoolRunner-ll 512-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the lowpower stand-by and dynamic operation, overall system reliability is improved This device consists of thirty two Function Blocks interconnected by a low power Advanced Interconnect Matrix(AlM).
The AlM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-tem PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.
Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds.A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input"registers to store signals directly from input pins.
Features
· Optimized for 1.8V systems
As fast as 7.1 ns pin-to-pin delays
As low as 14 uA quiescent current
· Industry's best 0.18 micron CMOS CPLD
Optimized architecture for effective logic synthesis
Multi-voltage /O operation -1.5V to 3.3V
· Available in multiple package options
208-pin PQFP with 173 user I/O
256-ball FT(1.0mm) BGA with 212 user I/O
324-ball FG(1.0mm) BGA with 270 user I/O
Pb-free available for all packages
· Advanced system features
Fastest in system programming
·1.8V ISP using IEEE 1532(JTAG) interface
IEEE1149.1 JTAG Boundary Scan Test
Optional Schmitt-trigger input(per pin)
Unsurpassed low power management DataGATE enable signal control
Four separate /O banks
RealDigital 100% CMOS product term generation
Flexible clocking modes Optional DualEDGE triggered registers Ciock divider(divide by 2,4,6,8,10,12,14,16)
CoolCLOCK
Global signal options with macrocell control
Multiple global clocks with phase selection per macrocell
Multiple global output enables Global set/reset
Advanced design security
PLA architecture
Superior pinout retention
100% product term routability across function block
Open-drain output option for Wired-OR and LED drive
Optional bus-hold,3-state or weak pullup on selected /O pins
Optional configurable grounds on unused /Os
Mixed I/O voltages compatible with 1.5V,1.8V,
2.5V, and 3.3V logic levels
SSTL2-1, SSTL3-1, and HSTL-1/0 compatiblility
· Hot Pluggable
• Optimized for 1.8V systems
- As fast as 7.1 ns pin-to-pin delays
- As low as 14 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in multiple package options
- 208-pin PQFP with 173 user I/O
- 256-ball FT (1.0mm) BGA with 212 user I/O
- 324-ball FG (1.0mm) BGA with 270 user I/O
- Pb-free available for all packages
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
· DataGATE enable signal control
- Four separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (divide by 2,4,6,8,10,12,14,16)
· CoolCLOCK
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Advanced design security
- PLA architecture
· Superior pinout retention
· 100% product term routability across function block
- Open-drain output option for Wired-OR and LED drive
- Optional bus-hold, 3-state or weak pullup on selected I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
- Hot Pluggable
Xilinx is a leading provider of programmable logic devices and associated technologies. As a top producer of programmable FPGAs, SoCs, MPSoCs, and 3D ICs, Xilinx has expanded quickly. Software defined and hardware optimized applications are supported by Xilinx, advancing the fields of cloud computing, SDN/NFV, video/vision, industrial IoT, and 5G wireless.
One of Xilinx's key innovations is the development of the Xilinx Vivado Design Suite, a comprehensive software toolchain used for designing and programming their FPGAs and SoCs. This suite provides developers with the necessary tools to create, simulate, and implement their designs on Xilinx devices.
In October 2020, Xilinx was acquired by Advanced Micro Devices (AMD), a major player in the semiconductor industry. This acquisition has enabled AMD to enhance its product portfolio and expand its offerings into the rapidly growing FPGA market.