Manufacturer | Xilinx |
Mounting Type | Surface Mount |
Number of I/O | 212 |
Package / Case | 256-LBGA |
Product Status | Active |
Number of Gates | 12000 |
Programmable Type | In System Programmable |
Number of Macrocells | 512 |
Delay Time tpd(1) Max | 9.2 ns |
Operating Temperature | -40°C ~ 85°C (TA) |
Supplier Device Package | 256-FTBGA (17x17) |
Voltage Supply - Internal | 1.7V ~ 1.9V |
Number of Logic Elements/Blocks | 32 |
- Guaranteed 20 year data retention
Family Overview
Xilinx CoolRunner™-II CPLDs deliver the high speed and ease of use associated with the XC9500/XL/XV CPLD family with the extremely low power versatility of the XPLA3 family in a single CPLD. This means that the exact same parts can be used for high-speed data communications/ computing systems and leading edge portable products, with the added benefit of In System Programming. Low power consumption and high-speed operation are combined into a single family that is easy to use and cost effective. Clocking techniques and other power saving features extend the users’ power budget. The design features are supported starting with Xilinx ISE® 4.1i WebPACK tool. Additional details can be found in Further Reading,
The Xilinx Embedded - CPLDs (Complex Programmable Logic Devices) series XC2C512-10FT256I is 512 MACROCELL 1.8V ZERO POWER ISP CPLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products. • Optimized for 1.8V systems
- As fast as 7.1 ns pin-to-pin delays
- As low as 14 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in multiple package options
- 208-pin PQFP with 173 user I/O
- 256-ball FT (1.0mm) BGA with 212 user I/O
- 324-ball FG (1.0mm) BGA with 270 user I/O
- Pb-free available for all packages
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
· DataGATE enable signal control
- Four separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (divide by 2,4,6,8,10,12,14,16)
· CoolCLOCK
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Advanced design security
- PLA architecture
· Superior pinout retention
· 100% product term routability across function block
- Open-drain output option for Wired-OR and LED drive
- Optional bus-hold, 3-state or weak pullup on selected I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
- Hot Pluggable
Xilinx is a leading provider of programmable logic devices and associated technologies. As a top producer of programmable FPGAs, SoCs, MPSoCs, and 3D ICs, Xilinx has expanded quickly. Software defined and hardware optimized applications are supported by Xilinx, advancing the fields of cloud computing, SDN/NFV, video/vision, industrial IoT, and 5G wireless.
One of Xilinx's key innovations is the development of the Xilinx Vivado Design Suite, a comprehensive software toolchain used for designing and programming their FPGAs and SoCs. This suite provides developers with the necessary tools to create, simulate, and implement their designs on Xilinx devices.
In October 2020, Xilinx was acquired by Advanced Micro Devices (AMD), a major player in the semiconductor industry. This acquisition has enabled AMD to enhance its product portfolio and expand its offerings into the rapidly growing FPGA market.