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ORT82G5-2F680C
- Part Number: ORT82G5-2F680C
- Categories:
- Manufacturer: Lattice Semiconductor Corporation
- MOQ: 1PCS
- In Stock: N/A
- Datasheet:
- Description: IC FPGA 372 I/O 680FBGA
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- Delivery Method: UPS/DHL/FEDEX/EMS
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Specifications
ORT82G5-2F680C details
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Datasheets
ORT82G5-2F680C Specifications
| Manufacturer | Lattice Semiconductor Corporation |
| Mounting Type | Surface Mount |
| Number of I/O | 372 |
| Package / Case | 680-BBGA |
| Product Status | Obsolete |
| Total RAM Bits | 113664 |
| Number of Gates | 643000 |
| Voltage - Supply | 1.425V ~ 3.6V |
| Number of LABs/CLBs | - |
| Operating Temperature | 0°C ~ 70°C (TA) |
| Supplier Device Package | 680-FPBGA (35x35) |
| Number of Logic Elements/Cells | 10368 |
ORT82G5-2F680C FPGAs Overview
The ORT42G5 and ORT82G5-2F680C provide a clockless high-speed interface for interdevice communication on a board or across a backplane. The built-in clock recovery of the ORT42G5 and ORT82G5-2F680C allows for higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefifit from the backplane transceiver as a network termination device. The device supports embedded 8b/10b encoding/decoding and link state machines for 10 G Ethernet, and Fibre Channel.
The ORT82G5-2F680C is pinout compatible with a sister device, the ORSO82G5, which implements eight channels of SERDES with SONET scrambling and cell processing. The ORT42G5 is pin compatible with the ORSO42G5,which implements four channels of SERDES with SONET scrambling and cell processing.
The Lattice Programmable Logic ICs series ORT82G5-2F680C is FPGA - Field Programmable Gate Array ORCA FPSC 2.7Gbits/s BP XCVR 643K, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com,
and you can also search for other FPGAs products.
Features
• High-performance programmable logic:
– 0.16 µm 7-level metal technology.
– Internal performance of >250 MHz.
– Over 400K usable system gates.
– Meets multiple I/O interface standards.
– 1.5V operation (30% less power than 1.8V operation) translates to greater performance.
• Traditional I/O selections:
– LVTTL (3.3V) and LVCMOS (2.5V and 1.8V) I/Os.
– Per pin-selectable I/O clamping diodes provide 3.3V PCI compliance.
– Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA
sink/3 mA source.
– Two slew rates supported (fast and slew-limited).
– Fast-capture input latch and input Flip-Flop (FF)/latch for reduced input setup time and zero hold time.
– Fast open-drain drive capability.
– Capability to register 3-state enable signal.
– Off-chip clock drive capability.
– Two-input function generator in output path
• New programmable high-speed I/O:
– Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, IV), ZBT, and DDR.
– Double-ended: LVDS, bused-LVDS, and LVPECL. Programmable (on/off) internal parallel termination (100
Ω) is also supported for these I/Os.
• New capability to (de)multiplex I/O signals:
– New DDR on both input and output at rates up to 350 MHz (700 MHz effective rate).
– New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O).
• Enhanced twin-block Programmable Function Unit (PFU):
– Eight 16-bit Look-Up Tables (LUTs) per PFU.
– Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act independently, plus one extra for arithmetic operations.
– New register control in each PFU has two independent programmable clocks, clock enables, local SET/RESET, and data selects.
– New LUT structure allows flflexible combinations of LUT4, LUT5, new LUT6, 4 → 1 MUX, new 8 → 1 MUX, and ripple mode arithmetic functions in the same PFU.
– 32 x 4 RAM per PFU, confifigurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the Supplemental Logic and Interconnect Cell (SLIC) decoders as bank drivers.
– Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing which reduces routing congestion and improves speed.
– Flexible fast access to PFU inputs from routing.
– Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out.
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ORT82G5-2F680C Packaging
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