OR3L165B8BM680-DB

OR3L165B8BM680-DB FPGAs Overview

This data addendum refers to the information found in the ORCA Series 3C and 3T Field-Programmable Gate Arrays Data Sheet. The Lattice Programmable Logic ICs series OR3L165B8BM680-DB is FPGA - Field Programmable Gate Array 8192 LUT 516 I/O, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

■High-performance, cost-effective, 0.25 um 5-level metal technology.

■2.5 V internal supply voltage and 3.3 V WO supply voltage for speed and compatibility.

■Up to 340,000 usable gates in 0.25 μm.

■Up to 612 user I/Os in 0.25 μm. (OR3L .xxxB l/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per pin basis, when usIng 3.3 V IO supply.)

■Twin-quad programmable tunction unit (PFU)architecture With eight 1 6-bit look-up tables (LUTs)per PFU, organized in two nibbles for use in nibble-or byte-wide functions. Allows for mixed arithmetic and logic functions in a single PFU.

■Nine user registers per PFU, one following each LUT, plus one extra. All have programmable clock enable and local set/reset, plus a global set/reset that can be disabled per PFU.

■Flexible input structure (FINS) of the PFUs provides a routability enhancement for LUTs with shared inputs and the logic flexibility of LUTs with independent inputs.

■Fast-carry logic and routing to adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out.
■Softwired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU.
■Supplemental logic and interconnect cell (SLIC) provides 3-statable buffers, up to 10-bit decoder,and PAL'like AND-OR-INVERT (AOI) in each programmable logic cell (PLC).
■Abundant hierarchical routing resources based on routing two data nibbles and two control lines per set provide ftor faster place and route implementations and less routing delay.
■Indivldually programmable drive capabillty: 12 mA sink/6 mA source or 6 mA sink/3 mA source.
■Buit-In boundary scan (IEEE↑1149.1 JTAG) and testability function to 3-state all /O pins.
■Enhanced system clock routing for low-skew. high-speed clocks originating on-chip or at any /O.
■Up to four ExpressCLK inputs allow extremely tast clocking of signals on- and off-chip plus access to internal general clock routing.
■StopCLK feature to glitchlessly stop/start the ExpressCLKs independently by user command.