LCMXO3L-9400E-5MG256C

LCMXO3L-9400E-5MG256C FPGAs Overview

MachXO3 device family is an Ultra-Low Density family that supports the most advanced programmable bridging and IO expansion. It has the breakthrough IO density and the lowest cost per IO. The device IO features have the integrated support for latest industry standard IO.

The MachXO3L/LF family of low power, instant-on, non-volatile PLDs has five devices with densities ranging from 640 to 9400 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. MachXO3LF devices also support User Flash Memory (UFM). These features allow these devices to be used in low cost, high volume consumer and system applications.

The MachXO3L/LF devices are designed on a 65nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power for all members of the family.

The MachXO3L/LF devices are available in two versions C and E with two speed grades: -5 and -6, with -6 being the fastest. C devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V. E devices only accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage both C and E are functionally compatible with each other.

The MachXO3L/LF PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving 2.5 x 2.5 mm WLCSP to the 19 x 19 mm caBGA. MachXO3L/LF devices support density migration within the same package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters

The MachXO3L/LF devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a “per-pin” basis. A userprogrammable internal oscillator is included in MachXO3L/LF devices. The clock output from this oscillator may be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and similar state machines. The MachXO3L/LF devices also provide flexible, reliable and secure configuration from on-chip NVCM/Flash. These devices can also configure themselves from external SPI Flash or be configured by an external master through the JTAG test access port or through the I2C port. Additionally, MachXO3L/LF devices support dual-boot capability (using external Flash memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the MachXO3L/LF family of devices. Popular logic synthesis tools provide synthesis library support for MachXO3L/LF. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the MachXO3L/LF device. These tools extract the timing from the routing and back-annotate it into the design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE modules, including a number of reference designs licensed free of charge, optimized for the MachXO3L/LF PLD family. By using these configurable soft core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity.

The Lattice Embedded - FPGAs (Field Programmable Gate Array) series LCMXO3L-9400E-5MG256C is IC FPGA 206 I/O 256CSFBGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

1.1.1. Solutions

 Smallest footprint, lowest power, high data throughput bridging solutions for mobile applications

 Optimized footprint, logic density, IO count, IO performance devices for IO management and logic applications

 High IO/logic, lowest cost/IO, high IO devices for IO expansion applications

1.1.2. Flexible Architecture

 Logic Density ranging from 64 to 9.4K LUT4

 High IO to LUT ratio with up to 384 IO pins

1.1.3. Advanced Packaging

 0.4 mm pitch: 1K to 4K densities in very small footprint WLCSP (2.5 mm × 2.5 mm to 3.8 mm × 3.8 mm) with 28 to 63 IOs

 0.5 mm pitch: 640 to 9.4K LUT densities in 6 mm x 6 mm to 10 mm x 10 mm BGA packages with up to 281 IOs

 0.8 mm pitch: 1K to 9.4K densities with up to 384 IOs in BGA packages

1.1.4. Pre-Engineered Source Synchronous I/O

 DDR registers in I/O cells

 Dedicated gearing logic

 7:1 Gearing for Display I/Os

 Generic DDR, DDRx2, DDRx4

1.1.5. High Performance, Flexible I/O Buffer

 Programmable sysIO buffer supports wide range of interfaces:

 LVCMOS 3.3/2.5/1.8/1.5/1.2

 LVTTL

 LVDS, Bus-LVDS, MLVDS, LVPECL

 MIPI D-PHY Emulated

 Schmitt trigger inputs, up to 0.5 V hysteresis

 Ideal for IO bridging applications

 I/Os support hot socketing

 On-chip differential termination

 Programmable pull-up or pull-down mode

1.1.6. Flexible On-Chip Clocking

 Eight primary clocks

 Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)

 Up to two analog PLLs per device with fractional-n frequency synthesis

 Wide input frequency range (7 MHz to 400 MHz).

1.1.7. Non-volatile, Multi-time Programmable

 Instant-on

 Powers up in microseconds

 Optional dual boot with external SPI memory

 Single-chip, secure solution

 Programmable through JTAG, SPI or I2C

 MachXO3L includes multi-time programmable NVCM

 MachXO3LF reconfigurable Flash includes 100,000 write/erase cycle

 Supports background programming of non-volatile memory

1.1.8. TransFR Reconfiguration

 In-field logic update while IO holds the system state

1.1.9. Enhanced System Level Support

 On-chip hardened functions: SPI, I2C, timer/counter

 On-chip oscillator with 5.5% accuracy

 Unique TraceID for system tracking

 Single power supply with extended operating range

 IEEE Standard 1149.1 boundary scan

 IEEE 1532 compliant in-system programming