ISPPAC-POWR607-01N32I

ISPPAC-POWR607-01N32I FPGAs Overview

The Power Manager II ispPAC-POWR607 is a generalpurpose power-supply monitor, reset generator and watchdog timer, incorporating both in-system programmable logic and analog functions implemented in nonvolatile E2 CMOS technology. The ispPAC-POWR607 device provides six independent analog input channels to monitor power supply voltages. Two general-purpose digital inputs are also provided for miscellaneous control functions.

The ispPAC-POWR607 provides up to seven open-drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and optocouplers, as well as for supervisory and general-purpose logic interface functions. Two of these outputs (HVOUT1-HVOUT2) can be configured as high-voltage MOSFET drivers. In high-voltage mode these outputs provide 9V for driving the gates of n-channel MOSFETs used as high-side power switches to control power supply ramp up and ramp down rate. The remaining five digital, open drain outputs can optionally be configured as digital inputs to sense more input signals as needed, such as manual reset, etc.

The diagram above shows how a ispPAC-POWR607 is used in a typical application. It controls power to the microprocessor system, generates the CPU reset and monitors critical power supply voltages, generating interrupts whenever faults are detected. It also provides a watchdog timer function to detect CPU operating and bus timeout errors.

The ispPAC-POWR607 incorporates a 16-macrocell CPLD. Figure 1 shows the analog input comparators and digital inputs used as inputs to the CPLD array. The digital output pins providing the external control signals are driven by the CPLD. Four independently program mable timers also interface with the CPLD and can create delays and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using LogiBuilder, an easy-to-learn language integrated into the PAC-Designer software. Control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs.

The Lattice Power Management ICs series ISPPAC-POWR607-01N32I is Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. I, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

 Power-Down Mode ICC < 10 µA

 Programmable Threshold Monitors

• Simultaneously monitors up to six power supplies

• Programmable analog trip points (1% step size; 192 steps)

• Programmable glitch filter

• Power-off detection (75 mV)

 Embedded Programmable Timers

• Four independent timers

• 32 µs to 2 second intervals for timing sequences

 Embedded PLD for Logical Control

• Rugged 16-macrocell CPLD architecture

• 81 product terms / 28 inputs

• Implements state machines and combinatorial functions

 Digital I/O

• Two dedicated digital inputs

• Five programmable digital I/O pins

 Two High-Voltage FET Drivers

• Power supply ramp up/down control

• Independently configurable for FET control or digital output

 Wide Supply Range (2.64 V to 3.96 V)

• In-system programmable through JTAG

• Industrial temperature range: –40 °C to +105 °C

• 24-pin and 32-pin QFNS packages, lead-free option