Manufacturer | Lattice Semiconductor Corporation |
PLL | Yes with Bypass |
Type | - |
Input | HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL |
Output | HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL |
Mounting Type | Surface Mount |
Package / Case | 48-LQFP |
Product Status | Obsolete |
Frequency - Max | 320MHz |
Voltage - Supply | 3V ~ 3.6V |
Divider/Multiplier | Yes/No |
Number of Circuits | 1 |
Ratio - Input:Output | 1:10 |
Operating Temperature | 0°C ~ 70°C |
Supplier Device Package | 48-TQFP (7x7) |
Differential - Input:Output | Yes/Yes |
■ 10MHz to 320MHz Input/Output Operation
■ Low Output to Output Skew (<50ps)
■ Low Jitter Peak-to-Peak (<60ps)
■ Up to 20 Programmable Fan-out Buffers
• Programmable output standards and individual enable controls
- LVTTL, LVCMOS, HSTL, SSTL, LVDS, LVPECL
• Programmable output impedance
- 40 to 70Ω in 5Ω increments
• Programmable slew rate
• Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.3V
■ Fully Integrated High-Performance PLL
• Programmable lock detect
• Multiply and divide ratio controlled by
- Input divider (5 bits)
- Feedback divider (5 bits)
- Five output dividers (5 bits)
• Programmable On-chip Loop Filter
■ Precision Programmable Phase Adjustment (Skew) Per Output
• 16 settings; minimum step size 195ps
- Locked to VCO frequency
• Up to +/- 12ns skew range
• Coarse and fine adjustment modes
■ Up to Five Clock Frequency Domains
■ Flexible Clock Reference and External Feedback Inputs
• Programmable input standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL
• Clock A/B selection multiplexer
• Feedback A/B selection multiplexer
• Programmable termination
■ Four User-programmable Profiles Stored in E2 CMOS Memory
• Supports both test and multiple operating configurations
■ Full JTAG Boundary Scan Test In-System Programming Support
■ Exceptional Power Supply Noise Immunity
■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
■ 100-pin and 48-pin TQFP Packages