ISPPAC30-01PI Specifications
Manufacturer | Renesas Electronics America Inc. |
Applications | - |
Mounting Type | - |
Package / Case | - |
Product Status | Active |
Voltage - Input | - |
Current - Supply | - |
Voltage - Supply | - |
Operating Temperature | - |
Supplier Device Package | - |
ISPPAC30-01PI FPGAs Overview
The ispPAC30 is a member of the Lattice family of InSystem Programmable (ISP) analog integrated circuits. It is digitally configured via SRAM and utilizes E2 CMOS memory for non-volatile storage of its configuration. The flexibility of ISP enables programming, verification and unlimited reconfiguration, directly on the printed circuit board.
The ispPAC30 is a complete front end solution for data acquisition applications using 10 to 12-bit ADC's. It provides multiple single-ended or differential signal inputs, multiplexing, precision gain, offset adjustment, filtering, and comparison functionality. It also has complete routability of inputs or outputs to any input cell and then from any input cell to either summing node of the two output amplifiers. Designers configure the ispPAC30 and verify its performance using PAC-Designer, an easy to use, Microsoft Windows compatible development tool. Device programming is supported using PC parallel port I/O operations.
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Features
■ Flexible Interface and Programming Control
• Full configuration capability, SPI or JTAG modes
• Unlimited device updates using SRAM register
• E2 CMOS for non-volatile configuration storage
• Real-time microcontroller configuration/control
■ Four Input Instrumentation Amplifiers (IA’s)
• High impedance: differential or single-ended
• 0V to 2.8V with programmable gains (±1 to ±10)
• Dual multiplexers (pin or serial port controlled)
• Connects easily to existing system circuits
■ Two Configurable Rail-to-Rail Output Amps
• Single-ended, 0V to 5V output swing
• Gain bandwidth product >15MHz
• Amplifier, filter, integrator or comparator modes
• 7 filter frequencies (50kHz to 600kHz)
■ Two, 4-Quadrant 8-Bit Multiplying DAC’s
• Full bandwidth when used as a multiplier
• Precision gain (<0.01 steps) with signal as input
• Precision offset (in 7 ranges) using internal Vref
■ Analog Input/Summation Routing Pools
• Routing of all I/O to any IA or MDAC
• Any IA/MDAC summed to either output amplifier
• Circuits with and without feedback possible
• Routable to maintain pin location relationships
■ Other Product Features
• Single supply (+5V) operation
• Precision voltage reference output (2.5V)
• Power-down for µWatt power consumption
• Auto-calibration of internal offsets
• Available in 28-pin PDIP or 24-pin SOIC
■ Applications
• Reconfigurable or adaptive signal conditioning
• Analog front end for most A/D converters
• Programmable analog signal control loops
• Precision programmable gain amplifiers
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