ISPLSI8840V-60LB492

ISPLSI8840V-60LB492 FPGAs Overview

The ispLSI 8840 device has seven Big Fast Megablocks for a total of 7 x 120 = 840 macrocells.

Each Big Fast Megablock has a total of 24 I/O cells and the Global Routing Plane has a total of 144 I/O cells. This gives (7 x 24) + 144 = 312 I/Os.

The total registers in the device is the sum of macrocells plus I/O cells, 840 + 312 = 1152 registers.

Features

• SuperBIG HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC

— 5V Power Supply

— 45,000 PLD Gates/840 Macrocells

— Up to 312 I/O Pins Supporting 3.3V/5V I/O

— 1152 Registers

— High-Speed Global and Big Fast Megablock (BFM) Interconnect

— Wide 20-Macrocell Generic Logic Block (GLB) for High Performance

— Wide Input Gating (44 Inputs per GLB) for Fast Counters, State Machines, Address Decoders, Etc.

— PCB-Efficient Ball Grid Array (BGA) Package Options

• HIGH-PERFORMANCE E2 CMOS TECHNOLOGY

— fmax = 110 MHz Maximum Operating Frequency

— tpd = 8.5 ns Propagation Delay

— TTL Compatible Inputs and 3.3V/5V Outputs

— PCI Compatible Inputs, Outputs and Speed Grades

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Programmable Speed/Power Logic Path Optimization

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 5V IN-SYSTEM PROGRAMMABLE

• ARCHITECTURE FEATURES

— Enhanced Pin-Locking Architecture, Symmetrical Generic Logic Blocks Connected by Hierarchical Big Fast Megablock and Global Routing Planes

— Product Term Sharing Array Supports up to 28 Product Terms per Macrocell Output

— Macrocells Support Concurrent Combinatorial and Registered Functions

— Embedded Tristate Bus Can Be Used as an Internal Tristate Bus or as an Extension of an External Tristate Bus

— Macrocell and I/O Registers Feature Multiple Control Options, Including Set, Reset and Clock Enable

— I/O Pins Support Programmable Bus Hold, Pull-Up, Open-Drain and Slew Rate Options

— Separate VCCIO Power Supply for Output Drivers Supports 5V or 3.3V Outputs

— I/O Cell Register Programmable as Input Register for Fast Setup Time or Output Register for Fast Clock to Output Time

• ispDesignEXPERT

– LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER

— PC and UNIX Platforms