HC1S80F1020AYR

HC1S80F1020AYR FPGAs Overview

HardCopy Stratix structured ASICs, Altera’s second-generation HardCopy structured ASICs, are low-cost, high-performance devices with the same architecture as the high-density Stratix FPGAs. The combination of Stratix FPGAs for prototyping and design verification, HardCopy Stratix devices for high-volume production, and the Quartus II design software beginning with version 3.0, provide a complete and powerful alternative to ASIC design and development.

HardCopy Stratix HC1S80F1020AYR devices are architecturally equivalent and have the same features as the corresponding Stratix FPGA. They offer pin-to-pin compatibility using the same package as the corresponding Stratix FPGA prototype. Designers can prototype their design to verify functionality with Stratix FPGAs before seamlessly migrating the proven design to a HardCopy Stratix structured ASIC.

The Quartus II software provides a complete set of inexpensive and easy-to-use tools for designing HardCopy Stratix devices. Using the successful and proven methodology from HardCopy APEX devices, Stratix HC1S80F1020AYR FPGA designs can be seamlessly and quickly migrated to a low-cost ASIC alternative. Designers can use the Quartus II software to design HardCopy Stratix devices to obtain an average of 50% higher performance and up to 40% lower power consumption than can be achieved in the corresponding Stratix FPGAs. The migration process is fully automated, requires minimal customer involvement, and takes approximately eight weeks to deliver fully tested HardCopy Stratix prototypes.

Features

HardCopy Stratix devices are manufactured on the same 1.5-V, 0.13 μm all-layer-copper metal fabrication process (up to eight layers of metal) as the Stratix FPGAs.
■ Preserves the functionality of a configured Stratix device
■ Pin-compatible with the Stratix counterparts
■ On average, 50% faster than their Stratix equivalents
■ On average, 40% less power consumption than their Stratix equivalents
■ 25,660 to 79,040 LEs
■ Up to 5,658,408 RAM bits available
■ TriMatrix memory architecture consisting of three RAM block sizes to implement true dual-port memory and first-in-first-out (FIFO) buffers
■ Embedded high-speed DSP blocks provide dedicated implementation of multipliers, multiply-accumulate functions, and finite impulse response (FIR) filters
■ Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device which provide identical features as the FPGA counterparts, including spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, advanced multiplication, and phase shifting
■ Supports numerous single-ended and differential I/O standards
■ Supports high-speed networking and communications bus standards including RapidIO, UTOPIA IV, CSIX, HyperTransport technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4
■ Differential on-chip termination support for LVDS