Manufacturer | Lattice Semiconductor Corporation |
Mounting Type | Through Hole |
Number of I/O | - |
Package / Case | 24-DIP (0.300", 7.62mm) |
Product Status | Obsolete |
Number of Gates | - |
Programmable Type | EE PLD |
Number of Macrocells | 10 |
Delay Time tpd(1) Max | 10 ns |
Operating Temperature | 0°C ~ 75°C (TA) |
Supplier Device Package | 24-PDIP |
Voltage Supply - Internal | 4.75V ~ 5.25V |
Number of Logic Elements/Blocks | - |
The GAL20RA10B-10LP combines a high performance CMOS process with electrically erasable (E2 ) floating gate technology to provide the highest speed performance available in the PLD market. Lattice Semiconductor’s E2 CMOS circuitry achieves power levels as low as 75mA typical ICC which represents a substantial savings in power when compared to bipolar counterparts. E2 technology offers high speed (<100ms) erase times providing the ability to reprogram, reconfigure or test the devices quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL20RA10B-10LP is a direct parametric compatible CMOS replacement for the PAL20RA10 device.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacturing. Therefore, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
The Lattice SPLD - Simple Programmable Logic Devices series GAL20RA10B-10LP is High-Speed Asynchronous E2CMOS PLD Generic Array Logic⑩,SPLD - Simple Programmable Logic Devices 20 INPUT 10 OUTPUT 5 V LOW POWER 10ns, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.• HIGH PERFORMANCE E2CMOS TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 83.3 MHz
— 9 ns Maximum from Clock Input to Data Output
— TTL Compatible 8 mA Outputs
— UltraMOS Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typical Icc
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100 ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Independent Programmable Clocks
— Independent Asynchronous Reset and Preset
— Registered or Combinatorial with Polarity
— Full Function and Parametric Compatibility with PAL20RA10
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability