EPM570T100C3N

EPM570T100C3N FPGAs Overview

Introduction

The MAX® II family of instant-on, non-volatile CPLDs is based on a 0.18-µm, 6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices offer high I/O counts, fast performance, and reliable fitting versus other CPLD architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system programmability (ISP), MAX II devices are designed to reduce cost and power while providing programmable solutions for applications such as bus bridging, I/O expansion, power-on reset (POR) and sequencing control, and device configuration control.

Features

The MAX II CPLD has the following features: 

■ Low-cost, low-power CPLD 

■ Instant-on, non-volatile architecture 

■ Standby current as low as 25 µA 

■ Provides fast propagation delay and clock-to-output times 

■ Provides four global clocks with two clocks available per logic array block (LAB) 

■ UFM block up to 8 Kbits for non-volatile storage 

■ MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V 

■ MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels 

■ Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors 

■ Schmitt triggers enabling noise tolerant inputs (programmable per pin) 

■ I/Os are fully compliant with the Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz 

■ Supports hot-socketing 

■ Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 

■ ISP circuitry compliant with IEEE Std. 1532

Functional Description

MAX® II devices contain a two-dimensional row- and column-based architecture to implement custom logic. Row and column interconnects provide signal interconnects between the logic array blocks (LABs).

The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. The MultiTrack interconnect provides fast granular timing delays between LABs. The fast routing between LEs provides minimum timing delay for added levels of logic versus globally routed interconnect structures.

The MAX II device I/O pins are fed by I/O elements (IOE) located at the ends of LAB rows and columns around the periphery of the device. Each IOE contains a bidirectional I/O buffer with several advanced features. I/O pins support Schmitt trigger inputs and various single-ended standards, such as 66-MHz, 32-bit PCI, and LVTTL.

MAX II devices provide a global clock network. The global clock network consists of four global clock lines that drive throughout the entire device, providing clocks for all resources within the device. The global clock lines can also be used for control signals such as clear, preset, or output enable.

The INTEL Embedded - CPLDs (Complex Programmable Logic Devices) series EPM570T100C3N is CPLD MAX II Family 440 Macro Cells 304MHz 0.18um Technology 2.5V/3.3V 100Pin TQFP, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features