EP910PI-35

EP910PI-35 FPGAs Overview

The Altera Classic TM EP910PI-35 device offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology, Classic devices also have a Turbo-only version, which is described in this data sheet.

EP910PI-35 devices support 100% TTL emulation and can easily integrate multiple PAL- and GAL-type devices with densities ranging from 300 to 900 usable gates. The Classic family provides pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz. Classic devices are available in a wide range of packages, including ceramic dual in-line package (CerDIP), plastic dual in-line package (PDIP), plastic J-lead chip carrier (PLCC), ceramic J-lead chip carrier (JLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages.

EPROM-based Classic devices can reduce active power consumption without sacrificing performance. This reduced power consumption makes the Classic family well suited for a wide range of low-power applications.

EP910PI-35 devices are 100% generically tested devices in windowed packages and can be erased with ultra-violet (UV) light, allowing design changes to be implemented quickly.

Features

■ High-performance, 16-macrocell Classic EPLD

– Combinatorial speeds with tPD as fast as 10 ns

– Counter frequencies of up to 100 MHz

– Pipelined data rates of up to 125 MHz

■ Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins

■ EP610 and EP610I devices are pin-, function-, and programming file-compatible

■ Programmable clock option for independent clocking of all registers

■ Macrocells individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation

■ Available in the following packages (see Figure 7):

– 24-pin small-outline integrated circuit (plastic SOIC only)

– 24-pin ceramic and plastic dual in-line package (CerDIP and PDIP)

– 28-pin plastic J-lead chip carrier (PLCC)