EP3CLS100F484C8N

EP3CLS100F484C8N FPGAs Overview

Cyclone III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power consumption, Cyclone III EP3CLS100F484C8N device provides the ideal solution for your high-volume, low-power, and cost-sensitive applications. To address the unique design needs, Cyclone III device family offers the following two variants:

■ Cyclone III—lowest power, high functionality with the lowest cost

■ Cyclone III LS—lowest power FPGAs with security

With densities ranging from about 5,000 to 200,000 logic elements (LEs) and 0.5 Megabits (Mb) to 8 Mb of memory for less than ¼ watt of static power consumption, Cyclone III makes it easier for you to meet your power budget. Cyclone III LS EP3CLS100F484C8N devices are the first to implement a suite of security features at the silicon, software, and intellectual property (IP) level on a low-power and high-functionality FPGA platform. This suite of security features protects the IP from tampering, reverse engineering and cloning. In addition, Cyclone III LS EP3CLS100F484C8N devices support design separation which enables you to introduce redundancy in a single chip to reduce size, weight, and power of your application.

The INTEL FPGA - Field Programmable Gate Array series EP3CLS100F484C8N is FPGA - Field Programmable Gate Array FPGA - Cyclone III 6278 LABs 294 IOs, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

Design Security Feature

Cyclone III LS devices offer the following design security features:

■ Configuration security using advanced encryption standard (AES) with 256-bit volatile key

■ Routing architecture optimized for design separation flow with the Quartus II software

■ Design separation flow achieves both physical and functional isolation between design partitions

■ Ability to disable external JTAG port

■ Error Detection (ED) Cycle Indicator to core

■ Provides a pass or fail indicator at every ED cycle

■ Provides visibility over intentional or unintentional change of configuration random access memory (CRAM) bits

■ Ability to perform zeroization to clear contents of the FPGA logic, CRAM, embedded memory, and AES key

■ Internal oscillator enables system monitor and health check capabilities