EP2C70F672C6N
- Part Number: EP2C70F672C6N
- Categories:
- Manufacturer: Intel
- MOQ: 1PCS
- In Stock: 5035
- Datasheet:
- Description: IC FPGA 422 I/O 672FBGA
- Payment method: Paypal/Wire transfer/Stripe/ Visa/Mastercard/AMEX
- Delivery Method: Ship within 12 hours
- 1 Pcs$324.904
- 10 Pcs$309.432
- 100 Pcs$294.697
- 1000 Pcs$288.919
- 10000 Pcs$288.919
| Manufacturer | Intel |
| Mounting Type | Surface Mount |
| Number of I/O | 422 |
| Package / Case | 672-BGA |
| Product Status | Active |
| Total RAM Bits | 1152000 |
| Number of Gates | - |
| Voltage - Supply | 1.15V ~ 1.25V |
| Number of LABs/CLBs | 4276 |
| Operating Temperature | 0°C ~ 85°C (TJ) |
| Supplier Device Package | 672-FBGA (27x27) |
| Number of Logic Elements/Cells | 68416 |
EP2C70F672C6N FPGAs Overview
FeaturesThe Cyclone II device family offers the following features:
■ High-density architecture with 4,608 to 68,416 LEs● M4K embedded memory blocks
● Up to 1.1 Mbits of RAM available without reducing available logic
● 4,096 memory bits per block (4,608 bits per block including 512 parity bits)
● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
● True dual-port (one read and one write, two reads, or two writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes
● Byte enables for data input masking during writes
● Up to 260-MHz operation
■ Embedded multipliers
● Up to 150 18- × 18-bit multipliers are each configurable as two independent 9- × 9-bit multipliers with up to 250-MHz performance
● Optional input and output registers
■ Advanced I/O support
● High-speed differential I/O standard support, including LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL
● Single-ended I/O standard support, including 2.5-V and 1.8-V, SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-, and 1.8-V LVTTL
● Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V operation at 33 or 66 MHz for 32- or 64-bit interfaces
● PCI Express with an external TI PHY and an Altera PCI Express ×1 Megacore® function
● 133-MHz PCI-X 1.0 specification compatibility
● High-speed external memory support, including DDR, DDR2, and SDR SDRAM, and QDRII SRAM supported by drop in Altera IP MegaCore functions for ease of use
● Three dedicated registers per I/O element (IOE): one input register, one output register, and one output-enable register
● Programmable bus-hold feature
● Programmable output drive strength feature
● Programmable delays from the pin to the IOE or logic array
● I/O bank grouping for unique VCCIO and/or VREF bank settings
● MultiVolt™ I/O standard support for 1.5-, 1.8-, 2.5-, and 3.3-interfaces
● Hot-socketing operation support
● Tri-state with weak pull-up on I/O pins before and during configuration
● Programmable open-drain outputs
● Series on-chip termination support
■ Flexible clock management circuitry
● Hierarchical clock network for up to 402.5-MHz performance
● Up to four PLLs per device provide clock multiplication and division, phase shifting, programmable duty cycle, and external clock outputs, allowing system-level clock management and skew control
● Up to 16 global clock lines in the global clock network that drive throughout the entire device
■ Device configuration
● Fast serial configuration allows configuration times less than 100 ms
● Decompression feature allows for smaller programming file storage and faster configuration times
● Supports multiple configuration modes: active serial, passive serial, and JTAG-based configuration
● Supports configuration through low-cost serial configuration devices
● Device configuration supports multiple voltages (either 3.3, 2.5, or 1.8 V)
■ Intellectual property
● Altera megafunction and Altera MegaCore function support, and Altera Megafunctions Partners Program (AMPPSM) megafunction support, for a wide range of embedded processors, on-chip and off-chip interfaces, peripheral functions, DSP functions, and communications functions and protocols. Visit the Altera IPMegaStore at www.altera.com to download IP MegaCore functions.
● Nios II Embedded Processor support
Functional Description
Cyclone® II devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between logic array blocks (LABs), embedded memory blocks, and embedded multipliers.
The logic array consists of LABs, with 16 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. Cyclone II devices range in density from 4,608 to 68,416 LEs.
Cyclone II devices provide a global clock network and up to four phase-locked loops (PLLs). The global clock network consists of up to 16 global clock lines that drive throughout the entire device. The global clock network can provide clocks for all resources within the device, such as input/output elements (IOEs), LEs, embedded multipliers, and embedded memory blocks. The global clock lines can also be used for other high fan-out signals. Cyclone II PLLs provide general-purpose clocking with clock synthesis and phase shifting as well as external outputs for high-speed differential I/O support.
M4K memory blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 260 MHz. These blocks are arranged in columns across the device in between certain LABs. Cyclone II devices offer between 119 to 1,152 Kbits of embedded memory
Each embedded multiplier block can implement up to either two 9 × 9-bit multipliers, or one 18 × 18-bit multiplier with up to 250-MHz performance. Embedded multipliers are arranged in columns across the device
Each Cyclone II device I/O pin is fed by an IOE located at the ends of LAB rows and columns around the periphery of the device. I/O pins support various single-ended and differential I/O standards, such as the 66- and 33-MHz, 64- and 32-bit PCI standard, PCI-X, and the LVDS I/O standard at a maximum data rate of 805 megabits per second (Mbps) for inputs and 640 Mbps for outputs. Each IOE contains a bidirectional I/O buffer and three registers for registering input, output, and output-enable signals. Dual-purpose DQS, DQ, and DM pins along with delay chains (used to phase-align double data rate (DDR) signals) provide interface support for external memory devices such as DDR, DDR2, and single data rate (SDR) SDRAM, and QDRII SRAM devices at up to 167 MHz.
Features
FeaturesThe Cyclone II device family offers the following features:
■ High-density architecture with 4,608 to 68,416 LEs● M4K embedded memory blocks
● Up to 1.1 Mbits of RAM available without reducing available logic
● 4,096 memory bits per block (4,608 bits per block including 512 parity bits)
● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
● True dual-port (one read and one write, two reads, or two writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes
● Byte enables for data input masking during writes
● Up to 260-MHz operation
■ Embedded multipliers
● Up to 150 18- × 18-bit multipliers are each configurable as two independent 9- × 9-bit multipliers with up to 250-MHz performance
● Optional input and output registers
■ Advanced I/O support
● High-speed differential I/O standard support, including LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL
● Single-ended I/O standard support, including 2.5-V and 1.8-V, SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-, and 1.8-V LVTTL
● Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V operation at 33 or 66 MHz for 32- or 64-bit interfaces
● PCI Express with an external TI PHY and an Altera PCI Express ×1 Megacore® function
● 133-MHz PCI-X 1.0 specification compatibility
● High-speed external memory support, including DDR, DDR2, and SDR SDRAM, and QDRII SRAM supported by drop in Altera IP MegaCore functions for ease of use
● Three dedicated registers per I/O element (IOE): one input register, one output register, and one output-enable register
● Programmable bus-hold feature
● Programmable output drive strength feature
● Programmable delays from the pin to the IOE or logic array
● I/O bank grouping for unique VCCIO and/or VREF bank settings
● MultiVolt™ I/O standard support for 1.5-, 1.8-, 2.5-, and 3.3-interfaces
● Hot-socketing operation support
● Tri-state with weak pull-up on I/O pins before and during configuration
● Programmable open-drain outputs
● Series on-chip termination support
■ Flexible clock management circuitry
● Hierarchical clock network for up to 402.5-MHz performance
● Up to four PLLs per device provide clock multiplication and division, phase shifting, programmable duty cycle, and external clock outputs, allowing system-level clock management and skew control
● Up to 16 global clock lines in the global clock network that drive throughout the entire device
■ Device configuration
● Fast serial configuration allows configuration times less than 100 ms
● Decompression feature allows for smaller programming file storage and faster configuration times
● Supports multiple configuration modes: active serial, passive serial, and JTAG-based configuration
● Supports configuration through low-cost serial configuration devices
● Device configuration supports multiple voltages (either 3.3, 2.5, or 1.8 V)
■ Intellectual property
● Altera megafunction and Altera MegaCore function support, and Altera Megafunctions Partners Program (AMPPSM) megafunction support, for a wide range of embedded processors, on-chip and off-chip interfaces, peripheral functions, DSP functions, and communications functions and protocols. Visit the Altera IPMegaStore at www.altera.com to
download IP MegaCore functions.
● Nios II Embedded Processor support
Functional
Description
Cyclone® II devices contain a two-dimensional row- and column-based
architecture to implement custom logic. Column and row interconnects
of varying speeds provide signal interconnects between logic array
blocks (LABs), embedded memory blocks, and embedded multipliers.
The logic array consists of LABs, with 16 logic elements (LEs) in each
LAB. An LE is a small unit of logic providing efficient implementation of
user logic functions. LABs are grouped into rows and columns across the
device. Cyclone II devices range in density from 4,608 to 68,416 LEs.
Cyclone II devices provide a global clock network and up to four
phase-locked loops (PLLs). The global clock network consists of up to 16
global clock lines that drive throughout the entire device. The global clock
network can provide clocks for all resources within the device, such as
input/output elements (IOEs), LEs, embedded multipliers, and
embedded memory blocks. The global clock lines can also be used for
other high fan-out signals. Cyclone II PLLs provide general-purpose
clocking with clock synthesis and phase shifting as well as external
outputs for high-speed differential I/O support.
M4K memory blocks are true dual-port memory blocks with 4K bits of
memory plus parity (4,608 bits). These blocks provide dedicated true
dual-port, simple dual-port, or single-port memory up to 36-bits wide at
up to 260 MHz. These blocks are arranged in columns across the device
in between certain LABs. Cyclone II devices offer between 119 to
1,152 Kbits of embedded memory
Each embedded multiplier block can implement up to either two 9 × 9-bit
multipliers, or one 18 × 18-bit multiplier with up to 250-MHz
performance. Embedded multipliers are arranged in columns across the
device
Each Cyclone II device I/O pin is fed by an IOE located at the ends of LAB
rows and columns around the periphery of the device. I/O pins support
various single-ended and differential I/O standards, such as the 66- and
33-MHz, 64- and 32-bit PCI standard, PCI-X, and the LVDS I/O standard
at a maximum data rate of 805 megabits per second (Mbps) for inputs and
640 Mbps for outputs. Each IOE contains a bidirectional I/O buffer and
three registers for registering input, output, and output-enable signals.
Dual-purpose DQS, DQ, and DM pins along with delay chains (used to phase-align double data rate (DDR) signals) provide interface support for
external memory devices such as DDR, DDR2, and single data rate (SDR)
SDRAM, and QDRII SRAM devices at up to 167 MHz.
step1: Inspect Products
step2: Vacuum Packaging
step3: Anti-Static Bag
step4: Individual Packing
step5: Packing Box
step6：Shipping Tag
- Before shipping, we will inspect the parts to ensure it in good condition and check that the parts are brand-new and original with the datasheet. And then, all the products will be packed in an anti-static bag.
- After ensuring that there are no issues with any of the goods after packing, we will wrap them carefully and send them by international express. It demonstrates exceptional seal integrity, outstanding tear and puncture resistance, and both.
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The following is an introduction to the characteristics of the thermocouple and thermistor temperature instruments. thermocouple Thermocouples are the most commonly used temperature sensors in temperature measurement. Its main advantages are a wide temperature range and adaptability to various atmospheric environments, and it is strong, low in price, does not require a power supply, and is the cheapest. A thermocouple consists of two wires of dissimilar metals (metal A and metal B) connected at one end. When one end of the thermocouple is heated, there is a potential difference in the thermocouple circuit. The temperature can be calculated from the measured potential difference. However, there is a nonlinear relationship between voltage and temperature. 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