EP20K400FC672-2

EP20K400FC672-2 FPGAs Overview

EP20K400FC672-2 of APEX 20K devices are the first PLDs designed with the MultiCore architecture, which combines the strengths of LUT-based and productterm-based devices with an enhanced memory structure. LUT-based logic provides optimized performance and efficiency for data-path, registerintensive, mathematical, or digital signal processing (DSP) designs.

Product-term-based logic is optimized for complex combinatorial paths, such as complex state machines. LUT- and product-term-based logic combined with memory functions and a wide variety of MegaCore and AMPP functions make the EP20K400FC672-2 device architecture uniquely suited for system-on-a-programmable-chip designs. Applications historically requiring a combination of LUT-, product-term-, and memory-based devices can now be integrated into one EP20K400FC672-2 device.

The INTEL FPGA - Field Programmable Gate Array series EP20K400FC672-2 is FPGA - Field Programmable Gate Array CPLD - APEX 20K 1664 Macros 502 IO, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

Flexible clock management circuitry with up to four phase-locked loops (PLLs)
– Built-in low-skew clock tree
– Up to eight global clock signals
– ClockLock feature reducing clock delay and skew
– ClockBoost feature providing clock multiplication and division
– ClockShiftTM programmable clock phase and delay shifting
■ Powerful I/O features
– Compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification,Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
– Support for high-speed external memories, including DDR SDRAM and ZBT SRAM (ZBT is a trademark of Integrated Device Technology, Inc.)
– Bidirectional I/O performance (tCO + tSU) up to 250 MHz
– LVDS performance up to 840 Mbits per channel
– Direct connection from I/O pins to local interconnect providing fast tCO and tSU times for complex logic
– MultiVolt I/O interface support to interface with 1.8-V, 2.5-V