EP20K300EFC672-2N

EP20K300EFC672-2N FPGAs Overview

APEXTM 20K EP20K300EFC672-2N devices are the first PLDs designed with the MultiCore architecture, which combines the strengths of LUT-based and productterm-based devices with an enhanced memory structure. LUT-based logic provides optimized performance and efficiency for data-path, registerintensive, mathematical, or digital signal processing (DSP) designs. Product-term-based logic is optimized for complex combinatorial paths, such as complex state machines. LUT- and product-term-based logic combined with memory functions and a wide variety of MegaCore and AMPP functions make the APEX 20K device architecture uniquely suited for system-on-a-programmable-chip designs. Applications historically requiring a combination of LUT-, product-term-, and memory-based devices can now be integrated into one APEX 20K device. 

The INTEL FPGA - Field Programmable Gate Array series EP20K300EFC672-2N is Field Programmable Gate Array CPLD - APEX 20K 1152 Macros 408 IO, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

■ Industry’s first programmable logic device (PLD) incorporating system-on-a-programmable-chip (SOPC) integration

– MultiCoreTM architecture integrating look-up table (LUT) logic, product-term logic, and embedded memory

– LUT logic used for register-intensive functions

– Embedded system block (ESB) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM)

– ESB implementation of product-term logic used for combinatorial-intensive functions