EP20K200CQ208C9

EP20K200CQ208C9 FPGAs Overview

EP20K200CQ208C9 devices of APEX 20K family are the first PLDs designed with the MultiCore architecture, which combines the strengths of LUT-based and productterm-based devices with an enhanced memory structure. LUT-based logic provides optimized performance and efficiency for data-path, registerintensive, mathematical, or digital signal processing (DSP) designs. Product-term-based logic is optimized for complex combinatorial paths, such as complex state machines.

LUT- and product-term-based logic combined with memory functions and a wide variety of MegaCore and AMPP functions make the EP20K200CQ208C9 device architecture uniquely suited for system-on-a-programmable-chip designs. Applications historically requiring a combination of LUT-, product-term-, and memory-based devices can now be integrated into one EP20K200CQ208C9 device.

Features

Industry’s first programmable logic device (PLD) incorporating system-on-a-programmable-chip (SOPC) integration

– MultiCoreTM architecture integrating look-up table (LUT) logic, product-term logic, and embedded memory

– LUT logic used for register-intensive functions

– Embedded system block (ESB) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM)

– ESB implementation of product-term logic used for combinatorial-intensive functions