EP1M120F484C7ES

EP1M120F484C7ES FPGAs Overview

Mercury EP1M120F484C7ES devices integrate high-speed differential transceivers and support for CDR with a speed-optimized PLD architecture. These transceivers are implemented through the dedicated serializer, deserializer, and clock recovery circuitry in the HSDI and incorporate support for the LVDS, LVPECL, and 3.3-V PCML I/O standards. This circuitry, together with enhanced I/O elements (IOEs) and support for numerous I/O standards, allows Mercury devices to meet high-speed interface requirements.

Mercury EP1M120F484C7ES are the first PLDs optimized for core performance. These LUT-based, enhanced memory devices use a network of fast routing resources to achieve optimal performance. These resources are ideal for data-path, register-intensive, mathematical, digital signal processing (DSP), or communications designs.

Features

System-level features

– Up to four general-purpose phase-locked loops (PLLs) with programmable multiplication and delay shifting

– Up to 12 PLL output ports

– Dedicated multiplier circuitry for high-speed implementation of signed or unsigned multiplication up to 16 × 16

– Embedded system blocks (ESBs) used to implement memory functions including quad-port RAM, true dual-port RAM, firstin first-out (FIFO) buffers, and content addressable memory (CAM)

– Each ESB contains 4,096 bits and can be split and used as two 2,048-bit unidirectional dual-port RAM blocks