Manufacturer | Rochester Electronics, LLC |
Mounting Type | Surface Mount |
Number of I/O | 120 |
Package / Case | 208-BFQFP |
Product Status | Obsolete |
Total RAM Bits | 12288 |
Number of Gates | 56000 |
Voltage - Supply | 2.375V ~ 2.625V |
Number of LABs/CLBs | 72 |
Operating Temperature | 0°C ~ 70°C (TA) |
Supplier Device Package | 208-PQFP (28x28) |
Number of Logic Elements/Cells | 576 |
Altera EP1K10QC208-2N devices provide a die-efficient, low-cost architecture by combining look-up table (LUT) architecture with EABs. LUT-based logic provides optimized performance and efficiency for data-path, register intensive, mathematical, or digital signal processing (DSP) designs, while EABs implement RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions. These elements make ACEX 1K suitable for complex logic functions and memory functions such as digital signal processing, wide data-path manipulation, data transformation and microcontrollers, as required in high-performance communications applications.
Based on reconfigurable CMOS SRAM elements, the EP1K10QC208-2N architecture incorporates all features necessary to implement common gate array megafunctions, along with a high pin count to enable an effective interface with system components. The advanced process and the low voltage requirement of the 2.5-V core allow EP1K10QC208-2N devices to meet the requirements of low-cost, high-volume applications ranging from DSL modems to low-cost switches.
The ability to reconfigure EP1K10QC208-2N devices enables complete testing prior to shipment and allows the designer to focus on simulation and design verification. EP1K10QC208-2N device reconfigurability eliminates inventory management for gate array designs and test vector generation for fault coverage.
Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip (SOPC) integration in a single device
– Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
– Dual-port capability with up to 16-bit width per embedded array block (EAB)
– Logic array for general logic functions
■ High density
– 10,000 to 100,000 typical gates (see Table 1)
– Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be used without reducing logic capacity)
■ Cost-efficient programmable architecture for high-volume applications
– Cost-optimized process
– Low cost solution for high-performance communications applications