A40MX04-PL68I

A40MX04-PL68I FPGAs Overview

Features

High Capacity 

• Single-Chip ASIC Alternative 

• 3,000 to 54,000 System Gates 

• Up to 2.5 kbits Configurable Dual-Port SRAM 

• Fast Wide-Decode Circuitry 

• Up to 202 User-Programmable I/O Pins

High Performance 

• 5.6 ns Clock-to-Out 

• 250 MHz Performance 

• 5 ns Dual-Port SRAM Access 

• 100 MHz FIFOs 

• 7.5 ns 35-Bit Address Decode

HiRel Features

 • Commercial, Industrial, and Military Temperature Plastic Packages 

• Commercial, Military Temperature and MIL-STD-883 Ceramic Packages 

• QML Certification 

• Ceramic Devices Available to DSCC SMD

Ease of Integration • Mixed Voltage Operation (5.0V or 3.3V I/O) 

• Synthesis-Friendly Architecture to Support ASIC Design Methodologies 

• Up to 100% Resource Utilization and 100% Pin Fixing 

• Deterministic, User-Controllable Timing 

• Unique In-System Diagnostic and Verification Capability with Silicon Explorer II 

• Low Power Consumption 

• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing 

• 5.0V and 3.3V Programmable PCI-Compliant I/O

General Description

Actel’s 40MX and 42MX families provide a high-performance, single-chip solution for shortening the system design and development cycle, offering a cost-effective alternative to ASICs. The 40MX and 42MX devices are excellent choices for integrating logic that is currently implemented in multiple PALs, CPLDs, and FPGAs. Example applications include high-speed controllers and address decoding, peripheral bus interfaces, DSP, and co-processor functions.

The MX device architecture is based on Actel’s patented antifuse technology implemented in a 0.45µ triple-metal CMOS process. With capacities ranging from 3,000 to 54,000 system gates, the synthesis-friendly MX devices provide performance up to 250 MHz, are live on power-up, and require up to five times lower stand-by power consumption than any other FPGA device. Actel’s MX FPGAs provide up to 202 user I/Os and are available in a wide variety of packages and speed grades.

Actel’s 42MX devices also feature MultiPlex I/Os, which support mixed voltage systems, enable programmable PCI, deliver high-performance operation at both 5.0V and 3.3V, and provide a low-power mode.

The MX PCI-Compliant devices are fully compliant with the PCI Local Bus Specification (version 2.1). They deliver 200 MHz on-chip operation and 6.1 ns clock-to-output performance with capacities spanning from 36,000 to 54,000 system gates. MX devices comply 100 percent to the electrical and timing specifications detailed in the PCI specification. However, as with all programmable logic devices, the performance of the final product depends upon the user's design and optimization techniques.

The MX24 and MX36 devices also include system-level features such as IEEE Standard 1149.1 (JTAG) Boudary Scan Testing, dual-port SRAM, and fast wide-decode modules. The A42MX36 device offers dual-port SRAM for implementing fast FIFOs, LIFOs, and temporary data storage. The large number of storage elements can efficiently address applications requiring wide datapath manipulation and can perform transformation functions such as those required for telecommunications, networking, and DSP. 

All products in the 40MX and 42MX families are available 100 percent tested over the military temperature range. In addition, the largest member of the family, the A42MX36, is available in both CQ208 and CQ256 ceramic packages screened to MIL-STD-883 levels. For easy prototyping and conversion from plastic to ceramic, the CQ208 and PQ208 devices are pin compatible.

The Microsemi FPGA - Field Programmable Gate Array series A40MX04-PL68I is MX FPGA 6K System Gates,FPGA - Field Programmable Gate Array (elektriskt programmerbar grindmatris) 6K System Gates, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at bitfoic.com, and you can also search for other FPGAs products.

Features

The following sections list out various features of the 42MX FPGA family devices.
High Capacity
• Single-Chip ASIC Alternative
• 3,000 to 54,000 System Gates
• Up to 2.5 kbits Configurable Dual-Port SRAM
• Fast Wide-Decode Circuitry
• Up to 202 User-Programmable I/O Pins
High Performance
• 5.6 ns Clock-to-Out
• 250 MHz Performance
• 5 ns Dual-Port SRAM Access
• 100 MHz FIFOs
• 7.5 ns 35-Bit Address Decode
HiRel Features
• Commercial, Industrial, Automotive, and Military Temperature Plastic Packages
• Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages
• QML Certification
• Ceramic Devices Available to DSCC SMD
Ease of Integration
• Mixed-Voltage Operation (5.0 V or 3.3 V for core and
I/Os), with PCI-Compliant I/Os
• Up to 100% Resource Utilization and 100% Pin Locking
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Verification Capability with Silicon Explorer II
• Low Power Consumption
• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing