The MACH" 4 family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer densities ranging from 32 to 256 macrocells with 100% utilization and 100% pin-out retention.The MACH 4 family offer 5-V (M4 xxx) and 3.3-V (M4LV-x8x) operation.MACH 4 products are 5-V or 3.3-V in-system programmable through the JTAG(IEEE Std.1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity. All MACH 4 family members deliver First -Time-Fit and easy system integration with pin-out retention after any design change and refit. For both 3.3-V and 5-V operation, MACH 4 products can deliver guaranteed fixed timing as fast as 75 ns, and 111 MHz feNT through the .SpeedLocking feature when using up to 20 produet terms per output (Table 2).

FUNCTIONAL DESCRIPTION

The fundamental architecture of MACH 4 devices (Figure 1) consists of multiple, optimized PAL blocks interconnected by a central switch matrix. The central switch matrix allows communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL blocks and central switch matrix allow the logic designer to create largedesigns in a single device instead of having to use multiple devices. The key to being able to make effective use of these deyices lies in the interconnect schemes. In MACH 4 architecture, the macrocells are flexibly coupled to the product terms through the logic allocator, and the I/O pins are flexibly coupled to the macrocells due to the output switch matrix. In addition, more input routing options are provided by the input switch matrix. These resources provide the flexibility needed to fit designs efficiently.

FEATURES 

◆High-performance, E2CMOS 3.3-V & 5-V CPLD families

◆Flexible architecture for rapid logic designs Excellent First-Time-Fit and refit feature

  - - SpeedLocking performance for guar anteed fixed timing Central, input and output switch matrices for 100% routability and 100% pin-out retention

◆High speed

  -7.5ns tpp Commercial and 10ns tpp Industrial

111.1MHz fcNτ

◆32 to 256 macrocells; 32 to 384 registers

◆44 to 256 pins in PLCC, PQFP, TQFP and BGA packages

◆Flexible architecture for a wide range of design styles D/T registers and latches,

  - Synchronous or asynchronous mode Dedicated input registers

  - Programmable polarity Reset/ preset swapping

◆Advanced capabilities for easy system integration

  3.3-V & 5-V JEDEC-compliant operations

  - JTAG (IEEE 1149.1) compliant for boundary scan testing

  3.3-V & 5-V JTAG in-system programming

  - PCI compliant (-71- 10/-12 speed grades)

  Safe for mixed supply voltage system designs

  Bus-FriendlyTM inputs and 1Os

  Programmable' security bit

  Individual output slew rate control

  Advanced E2CMOS process provides high-performance, cost-effective solutions

  Supported by ispDesignEXPERTM software for rapid logic development

  - - Supports HDL design methodologies with results optimized for MACH 4

  - Flexibility to adapt to user requirements

  Software partnerships that ensure customer success

◆Lattice and third-party hardware programming support

  - LatticePROTM software for in-system programmability support on PCs and automated test equipment

  Programming support on all major programmers including Data l/O, BP Microsystems, Advin,and System General